Analog MOSFET devices

Abstract

The specification describes MOS transistors for analog functions which have increased output impedance. The increased output impedance is the result of reduced drain depletion width. This is accomplished without adverse effects on other device parameters. The MOS transistor structures have an implant added to the lightly doped drain (LDD) with a conductivity type opposite to that of the LDD and a doping level higher than the channel doping. The added implant confines the spread of the depletion layer and reduces its width. A relatively small confinement results in a significant increase in output impedance of the device, and a corresponding increase in transistor gain.

We claim:  
     
       1. An improved silicon MOS transistor integrated circuit comprising a plurality of digital MOS transistor devices and a plurality of analog MOS transistor devices, each of said MOS transistor devices having an MOS gate with a gate threshold voltage V t  and an MOS channel beneath the MOS gate, said digital MOS transistor devices having a channel length equal to L, and said analog MOS transistor devices having a channel length greater than L, each of said analog MOS transistors having: 
       (a) a silicon substrate, said silicon substrate having a first conductivity type,  
       (b) a gate dielectric on said silicon substrate,  
       (c) a polysilicon gate on said gate dielectric,  
       (d) a lightly doped drain (LDD) region in said silicon substrate, said LDD region extending beneath said polysilicon gate by distance x,  
       (e) a depletion control implant region of said first conductivity type in said silicon substrate, said depletion control implant region extending beneath said polysilicon gate by distance y, where y>x and having an impurity level that changes the gate threshold voltage V t  by less than 50 mV,  
       (f) sidewall spacers on said silicon gate,  
       (g) source and drain regions in said silicon substrate,  
       (h) electrical contacts to said gate source and drain, and  
       (i) means for applying an analog signal to said silicon gate.  
     
     
       2. The MOS transistor integrated circuit of claim  1  wherein the silicon substrate is p-type. 
     
     
       3. The MOS transistor integrated circuit of claim  2  wherein the depletion control implant is boron with a dose in the range 1E13-1E14/cm 2 . 
     
     
       4. The MOS transistor integrated circuit of claim  3  wherein the LDD implant is arsenic with a dose in the range 5E13-5E14/cm 2 . 
     
     
       5. The MOS transistor integrated circuit of claim  3  wherein the LDD implant is phosphorus with a dose in the range 5E13-5E14/cm 2 . 
     
     
       6. The MOS transistor integrated circuit of claim  1  wherein the channel length of the analog transistors is greater than 0.7 μm.