Switching control circuit

Abstract

A switching regulator having a switching element, a control loop for varying a duty cycle of the switching element according to a difference between a switching regulator output electric quantity and a target output electric quantity, and a digital soft start-up circuit for digitally controlling the duty cycle of the switching element, independently from said difference, in a start-up phase of the switching regulator operation.

What is claimed is:  
     
       1. A switching regulator, comprising: a switching element and a control loop for varying a duty cycle of the switching element according to a difference between a switching regulator output electric quantity and a target output electric quantity, and a digital soft start-up circuit for digitally controlling the duty cycle of the switching element, independently from said difference, in a start-up phase of the switching regulator operation, said control loop including an error amplifier for generating an error signal indicative of said difference between the switching regulator output electric quantity and the target output electric quantity, and an error-to-duty cycle converter circuit for generating a drive signal for the switching element, said drive signal having a variable duty cycle depending on the error signal. 
     
     
       2. The switching regulator of claim  1 , comprising a multiplexer circuit for selectively supplying to the switching element either the drive signal or, during the start-up phase, a start-up drive signal generated by the digital soft start-up circuit. 
     
     
       3. The switching regulator of claim  2 , wherein the multiplexer circuit is controlled by a start-up enable signal generated by the digital start-up circuit. 
     
     
       4. The switching regulator of claim  3 , wherein the digital soft start-up circuit, at the beginning of the start-up phase, sets a duty cycle of the start-up drive signal to an initial low duty cycle value, lower than a duty cycle value that would correspond to said difference between the switching regulator output electric quantity and the target output electric quantity. 
     
     
       5. The switching regulator of claim  4 , wherein during the start-up phase the digital soft start-up circuit sets the duty cycle of the start-up drive signal to progressively increasing duty cycle values from said initial low duty cycle value. 
     
     
       6. The switching regulator of claim  4 , wherein the digital soft start-up circuit comprises a first clock signal having a first period and a second clock signal having a second period lower than the first period, the start-up drive signal having a period corresponding to the first period, the duty cycle of start-up drive signal increasing in discrete steps corresponding to the second period. 
     
     
       7. The switching regulator of claim  6 , wherein the number of said discrete steps is a first programmable parameter of the digital soft start-up circuit. 
     
     
       8. The switching regulator of claim  7 , wherein the digital soft start-up circuit, between successive increases of the start-up drive signal duty cycle, is configured to keep the duty cycle of the start-up signal constant for a number of periods determined by a second programmable parameter. 
     
     
       9. The switching regulator of claim  1 , wherein the digital startup circuit comprises a digital-to-analog converter that supplies the error amplifier with a clamping voltage for clamping the error signal and consequently limiting the duty cycle of the drive signal. 
     
     
       10. The switching regulator of claim  9 , wherein the value of the clamping voltage supplied by the digital soft start-up circuit to the error amplifier is made to vary during the start-up phase so as to progressively increase the duty cycle of the drive signal. 
     
     
       11. The switching regulator of claim  10 , wherein the digital control circuit comprises a timing circuit, a control logic supplied by the timing circuit and a digital-to-analog converter controlled by the control logic for supplying the error amplifier with the clamping voltage whose value is progressively increased on a time basis furnished by the timing circuit. 
     
     
       12. The switching regulator of claim  11 , wherein the timing circuit is a digital counter. 
     
     
       13. A switch element controlled circuit, comprising: 
       a first conditioned incrementor having a clock input, an input for receiving first digital input signals, the first conditioned incrementor configured to generate a first periodic signal for a predetermined period of time upon activation;  
       a second conditioned incrementor having a clock input, a first input for receiving the first digital input signals, a second input for receiving second digital input signals, and a third input for receiving the first periodic signal from the first conditioned incrementor, the second conditioned incrementor configured to generate a first control signal; and  
       a control signal circuit having a first clock input and a second clock input configured to receive first and second clock input signals, respectively, a reset input for receiving a reset signal, the control signal circuit configured to generate a switch element control signal.  
     
     
       14. The switch element control circuit of claim  13 , wherein the clock input of the first conditioned incrementor is coupled to a first clock signal source and the clock input of the second conditioned incrementor is coupled to the first clock signal source. 
     
     
       15. The circuit of claim  14 , wherein the second conditioned incrementor is configured to generate the first control signal as a divided signal of the first periodic signal generated by the first conditioned incrementor. 
     
     
       16. The circuit of claim  15 , wherein the first conditioned incrementor is configured to output a periodic signal that is augmented by a unity every period of the first clock signal for a predetermined number of periods and then returning to zero. 
     
     
       17. The circuit of claim  16 , wherein the predetermined number of periods is determined by the first conditioned incrementor in response to the first digital input signals. 
     
     
       18. The circuit of claim  15 , wherein the second conditioned incrementor is configured to generate the first control signal that is set to a numeric value of one upon activation of a reset signal and then to be augmented by a unity every period of the first clock signal for a predetermined period of time. 
     
     
       19. The circuit of claim  18 , wherein the predetermined period of time of augmentation of the second conditioned incrementor is determined by the second conditioned incrementor in response to the second digital input signals.