Architecture and interconnect for programmable logic circuits

Abstract

An improved programmable logic device and interconnect architecture is provided. In one embodiment an interconnect network provides programmable routing between calls. In one embodiment the interconnect network includes first routing lines of a first level of routing lines, second routing lines of a second level of routing lines and third routing lines of a third level of routing lines. The first and second routing lines are programmably and bidirectionally coupled to the third routing lines such that signals are selectively driven from either the first or second routing lines to the third routing lines and signals are selectively driven from the third routing lines to the first routing lines and second routing lines.

What is claimed is:  
     
       1. A programmable logic device comprising: 
       a plurality of cells; and  
       an interconnect network coupled to the cells, comprising:  
       first routing lines of a first level of routing lines, wherein the first level of routing lines spans n logical blocks,  
       second routing lines of a second level of routing lines, wherein the second level of routing lines span m+n logical blocks where m is different from n, and  
       third routing lines of a third level of routing lines, said first and second routing lines programmably and directly bidirectionally coupled to the third routing lines, such that signals are selectively driven from either the first or second routing lines to the third routing lines and signals are selectively driven from third routing lines to the first routing lines and the second routing lines.  
     
     
       2. A programmable logic device comprising: 
       a plurality of cells; and  
       an interconnect network coupled to the cells, comprising:  
       first routing lines of a first level of routing lines, wherein the first level of routing lines spans n logical blocks,  
       second routing lines of a second level of routing lines, wherein the second level of routing lines spans k+m+n logical blocks where k is different from m and n and m is different from n, and  
       third routing lines of a third level of routing lines, said first and second routing lines programmably and directly bidirectionally coupled to the third routing lines, such that signals are selectively driven from either the first or second routing lines to the third routing lines and signals are selectively driven from third routing lines to the first routing lines and the second routing lines.  
     
     
       3. A programmable logic circuit comprising: 
       a first plurality of configurable cells organized in two dimensions, said configurable cells grouped into substantially same size regions to form a level of hierarchy;  
       a second plurality of configurable cells, located in proximity together to form a first region, comprising a subset of configurable cells of said first plurality of cells;  
       a first set of routing lines, spanning a dimension of said first region and configured to couple to input ports and output ports of configurable cells of said second plurality of configurable cells through a first set of switches, wherein an output port of a configurable cell of said second plurality of configurable cells is coupled to at least one input port of other configurable cells of the second plurality of configurable cells;  
       a third plurality of configurable cells comprising at least the configurable cells of said second plurality of configurable cells to form a second region larger than said first region;  
       a second set of routing lines, spanning a dimension of said second region and configured to couple to input ports and output ports of the configurable cells of said third plurality of configurable cells through a second set of switches, wherein an output port of a configurable cell of said third plurality of configurable cells selectively coupled to drive a first routing line of said second set of routing lines through said second set of switches;  
       a third set of switches, said first set of routing lines selectively coupled to said second set of routing lines through the third set of switches;  
       a fourth plurality of configurable cells comprising at least the configurable cells of said third plurality of configurable cells to form a third region larger than said second region; and  
       a second routing line of a third set of routing lines, spanning a dimension of said third region and configured to couple to drive at least a third routing line of said first set of routing lines and said first routing line through a fourth set of switches.  
     
     
       4. The programmable logic circuit as set forth in claim  3 , wherein the switches comprise components selected from the group consisting of switches, programmable passgates and program controlled drivers/receivers. 
     
     
       5. The programmable logic circuit as set forth in claim  3 , wherein said first routing line is selectively coupled to drive said second routing line through a switch. 
     
     
       6. The programmable logic circuit as set forth in claim  3 , wherein said third routing line is selectively coupled to drive said second routing line through a switch. 
     
     
       7. The programmable logic circuit as set forth in claim  3 , further comprising a fourth set of routing lines, routing lines of the fourth set of routing lines having different spans than routing lines of the third set of routing lines, said routing lines of the fourth set of routing lines being selectively coupled to said first and second sets of routing lines through said fourth set of switches. 
     
     
       8. The programmable logic circuit as set forth in claim  3 , further comprising a fifth set of switches selectively coupling routing lines of said third set of routing lines in a first dimension to routing lines of said third set of routing lines in a second dimension. 
     
     
       9. The programmable logic circuit as set forth in claim  3 , further comprising a sixth set of switches selectively coupling routing lines of said first sets of routing lines of two adjacent first regions. 
     
     
       10. The programmable logic circuit as set forth in claim  3 , further comprising a seventh set of switches selectively coupling routing lines of said second set of routing lines of two adjacent second regions. 
     
     
       11. The programmable logic circuit as set forth in claim  3 , further comprising an eighth set of switches selectively coupling routing lines of said third set of routing lines of two adjacent third regions. 
     
     
       12. The programmable logic circuit as set forth in claim  3 , further comprising a fourth routing line of said first set of routing lines to selectively couple a fifth routing line of said third set of routing lines through a first switch of said fourth set of switches and a sixth routing line of said third set of routing lines through a second switch of said fourth set of switches. 
     
     
       13. The programmable logic circuit as set forth in claim  12 , further comprising a seventh routing line of said second set of routing lines selectively coupling said fifth routing line through said first switch, and selectively coupling said sixth routing line through said second switch. 
     
     
       14. The programmable logic circuit as set forth in claim  7 , further comprising at least a fifth set of routing lines selectively coupled to said fourth set of routing lines through a ninth set of switches. 
     
     
       15. A programmable logic circuit comprising: 
       a first routing line, a second routing line, a third routing line, a fourth routing line, and a fifth routing line wherein said first, second, fourth and fifth routing lines have different spans;  
       said first routing line selectively coupling to the third routing line through a first switch;  
       said second routing line selectively coupling to the third routing line through a second switch;  
       said third routing line selectively coupling to the fourth routing line through a third switch; and  
       said third routing line selectively coupling to the fifth routing line through a fourth switch.  
     
     
       16. The programmable logic circuit as set forth in claim  15 , wherein the first, second, third, fourth, and fifth switches consist of components selected from the group comprising switches, programmable passgates and program controlled drivers/receivers. 
     
     
       17. The programmable logic circuit as set forth in claim  15 , wherein an output port of a configurable cell of a first plurality of configurable cells is selectively coupled to an input port of another configurable cell of said first plurality of configurable cells through said first routing line. 
     
     
       18. The programmable logic circuit as set forth in claim  15 , wherein an output port of a configurable cell of a second plurality of configurable cells, said second plurality of configurable cells comprising at least the configurable cells of said first plurality of configurable cells, is selectively coupled to an input port of another configurable cell of said second plurality of configurable cells through said second routing line. 
     
     
       19. The programmable logic circuit as set forth in claim  15 , further comprising a sixth routing line, said fourth and said sixth routing lines having equal spans, said sixth routing line selectively coupled to said third routing line through a fifth switch. 
     
     
       20. The programmable logic circuit as set forth in claim  15 , further comprising a seventh routing line along a different dimension from said fourth routing line, said fourth routing line selectively coupled to said seventh routing line through a sixth switch. 
     
     
       21. The programmable logic circuit as set forth in claim  15 , further comprising an eighth routing line parallel to said fourth routing line, said fourth routing line selectively coupled to said eighth routing line through a seventh switch. 
     
     
       22. A method for programming a programmable logic circuit comprising: 
       organizing a first plurality of configurable cells in two dimensions;  
       grouping the first plurality of configurable cells into substantially same size regions to form a level of hierarchy;  
       locating a second plurality of configurable cells in proximity to form a first region, the first region comprising a subset of configurable cells of said first plurality of cells;  
       selectively coupling input ports and output ports of configurable cells of the second plurality of configurable cells through a first set of routing lines spanning a dimension of said first region, wherein an output port of a configurable cell of said second plurality of configurable cells is coupled to at least one input port of other configurable cells of the second plurality of configurable cells;  
       locating a third plurality of configurable cells comprising at least the configurable cells of said second plurality of configurable cells to form a second region larger than said first region;  
       selectively coupling an output port of a configurable cells of the third plurality of configurable cells to drive a first routing line of a second set of routing lines, routing lines of the second set of routing lines spanning a dimension of the second;  
       selectively coupling the first set of routing lines to said second set of routing lines;  
       locating a fourth plurality of configurable cells comprising at least the configurable cells of said third plurality of configurable cells to form a third region larger than said second region; and  
       selectively coupling a second routing line of a third set of routing lines, spanning a dimension of said third region, to drive at least a third routing line of said first set of routing lines and said first routing line.  
     
     
       23. The method as set forth in claim  22 , further comprising selectively coupling the first routing line to drive said second routing line. 
     
     
       24. The method as set forth in claim  22 , further comprising selectively coupling said third routing line to drive said second routing line. 
     
     
       25. The method as set forth in claim  22 , further comprising further comprising selectively coupling a fourth set of routing lines, having different spans than said third set of routing lines, to said first and second sets of routing lines. 
     
     
       26. The method as set forth in claim  22 , further comprising selectively coupling routing lines of said third set of routing lines in a first dimension to routing lines of said third set of routing lines in a second dimension. 
     
     
       27. The method as set forth in claim  22 , further comprising selectively coupling routing lines of said first sets of routing lines of two adjacent first regions. 
     
     
       28. The method as set forth in claim  22 , further comprising selectively coupling routing lines of said second sets of routing lines of two adjacent second regions. 
     
     
       29. The method as set forth in claim  22 , further comprising selectively coupling routing lines of said third sets of routing lines of two adjacent third regions. 
     
     
       30. The method as set forth in claim  22 , further comprising selectively coupling a fourth routing line of the first set of routing lines to a fifth routing line of said third set of routing lines and sixth routing lines of said third set of routing lines. 
     
     
       31. The method as set forth in claim  30 , further comprising selectively coupling said fifth routing line and said sixth routing line through a seventh routing line of said second set of routing lines. 
     
     
       32. The method as set forth in claim  25 , further comprising selectively coupling at least a fifth set of routing lines to said fourth set of routing lines. 
     
     
       33. A method for programming a programmable logic circuit comprising: 
       providing a first routing line, a second routing line, a third routing line, a fourth routing line, and a fifth routing line wherein said first, second, fourth and fifth routing lines have different spans;  
       selectively coupling the first routing line to the third routing line;  
       selectively coupling said second routing line to the third routing line;  
       selectively coupling the third routing line to the fourth routing line; and  
       selectively coupling said third routing line to the fifth routing line.  
     
     
       34. The method as set forth in claim  33 , further comprising selectively coupling an output port of a configurable cell of a first plurality of configurable cells to an input port of another configurable cell of said first plurality of configurable cells through said first routing line. 
     
     
       35. The method as set forth in claim  33 , selectively coupling through said second routing line an output port of a configurable cell of a second plurality of configurable cells, said second plurality of configurable cells comprising at least the configurable cells of said first plurality of configurable cells, to an input port of another configurable cell of said second plurality of configurable cells. 
     
     
       36. The method as set forth in claim  33 , further comprising selectively coupling a sixth routing line, said fourth and said sixth routing lines having equal spans, to said third routing line. 
     
     
       37. The method as set forth in claim  33 , further comprising selectively coupling the fourth routing line to a seventh routing line along a different dimension from said fourth routing line. 
     
     
       38. The method as set forth in claim  33 , further comprising selectively coupling an eighth routing line parallel to said fourth routing line.