Nonvolatile semiconductor memory device and data writing method therefor

Abstract

In a nonvolatile semiconductor memory device wherein a plurality of threshold voltages are set so as to store multivalued information in one memory cell, data is first written into the memory cell whose threshold voltage is the lowest as a written state from the erase level, and data is successively written into memory cells whose threshold voltages are higher.

What is claimed is:  
     
       1. A nonvolatile semiconductor memory device comprising: 
       a plurality of data lines;  
       a plurality of word lines;  
       a plurality of memory cells, each of which is coupled to a corresponding data line and a corresponding word line, each of which includes a control gate and a floating gate, and each of which has a threshold voltage corresponding to data,  
       wherein each of said plurality of memory cells has a threshold voltage in a first threshold voltage region as an erase state by executing an erase operation and has the threshold voltage in one of said first threshold voltage region, a second threshold voltage region and a third threshold voltage region by executing a write operation, and  
       wherein an absolute value of the threshold voltage of said second threshold voltage region is between an absolute value of the threshold voltage of said first threshold voltage region and an absolute value of the threshold voltage of said third threshold voltage region;  
       a plurality of data latch each of which is coupled to a corresponding data line and each of which store data to be written in memory cells coupled to a selected word line; and  
       a write control circuit, which brings a threshold voltage of a first memory cell in said erase state and coupled to the selected word line to the threshold voltage in said third threshold voltage region and brings a threshold voltage of a second memory cell in said erase state and coupled to said selected word line in said second threshold voltage region thereafter, in accordance with data stored in said plurality of data latch, thereby to write in data corresponding to the threshold voltage in said third threshold voltage region to said first memory cell in said plurality of memory cells and to write in data corresponding to the threshold voltage in said second threshold voltage region to said second memory cell in said plurality of memory cells.  
     
     
       2. The nonvolatile semiconductor memory device according to claim  1 , 
       wherein said first threshold voltage region is higher than both said second threshold voltage region and said third threshold voltage region.  
     
     
       3. The nonvolatile semiconductor memory device according to claim  2 , 
       wherein a change in threshold voltage of each of said plurality of memory cells is achieved by using a tunnel phenomenon.  
     
     
       4. The nonvolatile semiconductor memory device comprising: 
       a plurality of data lines;  
       a plurality of word lines;  
       a plurality of memory cells, each of which is coupled to a corresponding data line and a corresponding word line, each of which includes a control gate and a floating gate, and each of which has a threshold voltage corresponding to data,  
       wherein each of said plurality of memory cells has one of a threshold voltage in a first threshold voltage region to be allocated as an erase state and a threshold voltage taken from among a plurality of threshold voltage regions which are, respectively, different from said first threshold voltage region and which are allocated as different write states;  
       a plurality of data latch each of which is coupled to a corresponding data line and each of which stores data to be written in memory cells coupled to a selected word line; and  
       a write control circuit controlling a writing operation for writing data stored in said plurality of data latch to memory cells coupled to the selected word line from said plurality of word lines,  
       wherein a threshold voltage of a memory cell coupled to the selected word line is shifted from said first threshold voltage region to a second threshold voltage region, which is allocated as a write state, and followed by the shifting of a threshold voltage of another memory cell coupled to said selected word line from said first threshold voltage region to a third threshold voltage region, which is allocated as another write state, said third threshold voltage region is nearer than said second threshold voltage region to said first threshold voltage region in voltage potential.  
     
     
       5. The nonvolatile semiconductor memory device according to claim  4 , 
       wherein said threshold voltages of said memory cells coupled to said selected word line are shifted, by said write control circuit, from said first threshold voltage region to threshold voltage regions allocated as write states in a successive order starting with the shifting of said threshold voltage of a first one of said memory cells whose threshold voltage is to be shifted to the threshold voltage region furthest away from said first threshold voltage region, followed with the shifting of said threshold voltage of a second one of said memory cells whose threshold voltage is to be shifted to said threshold voltage region which is the next-furthest from said first threshold voltage region, and so forth.  
     
     
       6. The nonvolatile semiconductor memory device according to claim  5 , further comprising a voltage generating circuit generating internal voltages, 
       wherein said write control circuit controls the applying an internal voltage of said internal voltages to a selected word line to perform said writing operation, and  
       wherein a value of said applied voltage to said selected word line is changed in accordance with said threshold voltage region to be changed.  
     
     
       7. The nonvolatile semiconductor memory device according to claim  6 , 
       wherein each of said plurality of memory cells stores 2 bits, and  
       wherein said plurality of threshold voltage regions include said second threshold voltage region, said third threshold voltage region and a fourth threshold voltage region and a memory cell has one of a threshold voltage in said first threshold voltage region, a threshold voltage in said second threshold voltage region, a threshold voltage in said third threshold voltage region and a threshold voltage in a fourth threshold voltage region to represent 2 bits.  
     
     
       8. The nonvolatile semiconductor memory device according to claim  7 , 
       wherein said writing control circuit brings a threshold voltage of a memory cell to one of said second threshold voltage region, said third threshold voltage region and said fourth threshold voltage region from said first threshold voltage region in response to inputting of a command for said writing operation.  
     
     
       9. The nonvolatile semiconductor memory device according to claim  8 , 
       wherein said writing control circuit includes a command decoder decoding said inputted command and a control circuit generating a control signal in accordance with output of said command decoder.  
     
     
       10. The nonvolatile semiconductor memory device according to claim  9 , 
       wherein said first threshold voltage region is higher than both said second threshold voltage region and said third threshold voltage region.  
     
     
       11. The nonvolatile semiconductor memory device according to claim  10 , 
       wherein a change in threshold voltage of each of said plurality of memory cells is achieved by using a tunnel phenomenon.  
     
     
       12. A nonvolatile semiconductor memory device comprising: 
       a plurality of data lines;  
       a plurality of word lines;  
       a plurality of memory cells, each of which is coupled to a corresponding data line and a corresponding word line, each of which includes a control gate and a floating gate, and each of which has a threshold voltage corresponding to multi-level data,  
       a plurality of data latch each of which is coupled to a corresponding data line and each of which stores data to be written in memory cells coupled to a selected word line; and  
       a write control circuit controlling a writing operation for writing data stored in said plurality of data latch to memory cells coupled to the selected word line from said plurality of word lines,  
       wherein a threshold voltage of a memory cell coupled to the selected word line is shifted from said first threshold voltage region, which is allocated as an erase state, to a second threshold voltage region, which is allocated as a write state, and followed by the shifting of a threshold voltage of another memory cell coupled to said selected word line from said first threshold voltage region to a third threshold voltage region, which is allocated as another write state, said third threshold voltage region is nearer than said second threshold voltage region to said first threshold voltage region in voltage potential.  
     
     
       13. The nonvolatile semiconductor memory device according to claim  12 , 
       wherein each of said plurality of memory cells has one of a threshold voltage in said first threshold voltage region to be allocated as said erase state and a threshold voltage taken from among a plurality of threshold voltage regions which are, respectively, different from said first threshold voltage region and which include said second threshold voltage region and said third threshold voltage region.  
     
     
       14. The nonvolatile semiconductor memory device according to claim  13 , 
       wherein said threshold voltages of said memory cells coupled to said selected word line are shifted, by said write control circuit, from said first threshold voltage region to threshold voltage regions allocated as write states in a successive order starting with the shifting of said threshold voltage of a first one of said memory cells whose threshold voltage is to be shifted to the threshold voltage region furthest away from said first threshold voltage region, followed with the shifting of said threshold voltage of a second one of said memory cells whose threshold voltage is to be shifted to said threshold voltage region which is the next-furthest from said first threshold voltage region, and so forth.  
     
     
       15. The nonvolatile semiconductor memory device according to claim  14 , further comprising a voltage generating circuit generating internal voltages, 
       wherein said write control circuit controls the applying an internal voltage of said internal voltages to a selected word line to perform said writing operation, and  
       wherein a value of said applied voltage to said selected word line is changed in accordance with said threshold voltage region to be changed.  
     
     
       16. The nonvolatile semiconductor memory device according to claim  15 , 
       wherein each of said plurality of memory cells stores 2 bits, and  
       wherein said plurality of threshold voltage regions include said second threshold voltage region, said third threshold voltage region and a fourth threshold voltage region and a memory cell has one of a threshold voltage in said first threshold voltage region, a threshold voltage in said second threshold voltage region, a threshold voltage in said third threshold voltage region and a threshold voltage in a fourth threshold voltage region to represent 2 bits.  
     
     
       17. The nonvolatile semiconductor memory device according to claim  16 , 
       wherein said writing control circuit brings a threshold voltage of a memory cell to one of said second threshold voltage region, said third threshold voltage region and said fourth threshold voltage region from said first threshold voltage region in response to inputting of a command for said writing operation.  
     
     
       18. The nonvolatile semiconductor memory device according to claim  17 , 
       wherein said writing control circuit includes a command decoder decoding said inputted command and a control circuit generating a control signal in accordance with output of said command decoder.  
     
     
       19. The nonvolatile semiconductor memory device according to claim  18 , 
       wherein said first threshold voltage region is higher than both said second threshold voltage region and said third threshold voltage region.  
     
     
       20. The nonvolatile semiconductor memory device according to claim  19 , 
       wherein a change in threshold voltage of each of said plurality of memory cells is achieved by using a tunnel phenomenon.