Logic circuits and carry-lookahead circuits

Abstract

Logic circuits and carry-lookahead circuits capable of performing high speed operations with simplified designs are described. The logic circuit is provided for searching a binary bit string from the most significant bit to the least significant bit for a first “0” or “1” bit and comprises a NOT gate circuit receiving the most significant bit of said binary bit string and composed of a dynamic logic circuit; NOR gate circuits provided in a one-to-one correspondence to the respective bits of said binary bit string, each NOR gate circuit receiving the bit of said binary bit string corresponding to the bit position of said each NOR gate circuit and, if any, the bit(s) of said binary bit string which is more significant than the bit corresponding to the bit position of said each NOR gate circuit except for the most significant bit; and two-input NOR gate circuits each of which receives two logic signals as output from adjacent ones of said NOT and NOR gate circuits.

What is claimed is:  
     
       1. A logic circuit for searching a binary bit string from the most significant bit to the least significant bit for a first “0” or “1” bit, said logic circuit comprising: 
       a NOT gate circuit receiving the most significant bit of said binary bit string and composed of a dynamic logic circuit;  
       NOR gate circuits provided in a one-to-one correspondence to the respective bits of said binary bit string, each NOR gate circuit receiving the bit of said binary bit string corresponding to the bit position of said each NOR gate circuit and, if any, the bit(s) of said binary bit string which is more significant than the bit corresponding to the bit position of said each NOR gate circuit except for the most significant bit; and  
       two-input NOR gate circuits each of which receives a first logic signal as output from one of said NOT and NOR gate circuits and a second logic signal as output from another of said NOT and NOR gate circuits which is adjacent said ones of said NOT and NOR gate circuits in the order of the bit position.  
     
     
       2. The logic circuit as claimed in claim  1  wherein said NOT and NOR gate circuits are composed of NMOS FETs connected in parallel between the ground level and the output lines of said NOT and NOR gate circuits. 
     
     
       3. The logic circuit as claimed in claim  1  wherein a plurality of inverters are provided in advance of said 2-input NOR gate circuits.