Charge pump circuit for a phase locked loop

Abstract

A charge pump circuit for a phase locked loop includes series-connected FETs in which a reference current flows and other series-connected FETs in which sourcing and sinking currents flow. The junctions of the two series-connected FETs are connected to the non-inverting and inverting input terminals of an operational amplifier. The amplifier detects the voltage difference between a reference side junction and the output voltage of the charge pump circuit and provides an amplified voltage of the detected voltage difference. In response to the amplified voltage, the charge pump circuit sources to and sinks current from an external circuit to which the charge pump circuit is connected. Due to the definite and high input impedance of the operational amplifier, there is no mismatch between the source and the sink currents. A start-up FET initializes the charge pump circuit so that current flows in the series-connected FETs.

What is claimed is:  
     
       1. A charge pump circuit for sourcing current to and sinking current from an external circuit, the charge pump circuit comprising: 
       first transistor means comprising first and second transistors, each having an input control electrode and two other electrodes, the other two electrodes of both transistors being connected in series, the series-connected first and second transistors causing a first current to flow therein upon application of operating voltage to the first transistor means which develops a first voltage in response to the first current;  
       second transistor means comprising third and fourth transistors, each having an input control electrode and two other electrodes, the other two electrodes of both transistors being connected in series, upon application of the operating voltage, the second transistor means causing a second current to flow in the third transistor and a third current to flow in the fourth transistor, a second voltage being developed across the external circuit in response to the second or third current;  
       first feedback means for providing a first signal in response to the first and second voltages, the first signal being fed to the input control electrode of the first transistor;  
       second feedback means for providing a second signal in response to a reference voltage and a third voltage, the second signal being fed to the input control electrode of the second transistor;  
       first feeding means for feeding the first signal to the input control electrode of the third transistor in response to a first input signal;  
       second feeding means for feeding the second signal to the input control electrode of the fourth transistor in response to a second input signal; and  
       start-up means for initializing the first transistor means so that a start-up current flows therein wherein the sourcing current is the second current, the sinking current is the third current, and the third voltage is from the first transistor means.  
     
     
       2. The charge pump circuit of claim  1 , wherein the start-up means comprises turn-on means for turning-on the first transistor to initialize the first transistor means. 
     
     
       3. The charge pump circuit of claim  2 , wherein the turn-on means comprises means for providing a turn-on signal in response to the voltage difference between a start reference voltage and the third voltage. 
     
     
       4. The charge pump circuit of claim  3 , wherein the first feedback means comprises first response means for providing the first signal, the voltage of which is proportional to the voltage difference between the first and second voltages, the first signal causing the first current to be varied. 
     
     
       5. The charge pump circuit of claim  4 , wherein the first response means comprises a first operational amplifier having non-inverting and inverting input terminals for receiving the first and second voltages, respectively and an output terminal for providing the first signal, the first operational amplifier varying the first signal so that the first and second voltages are matched. 
     
     
       6. The charge pump circuit of claim  5 , wherein the second feedback means comprises second response means for providing the second signal, the voltage of which is proportional to the voltage difference between the reference voltage and the third voltage, the third voltage corresponding to the first voltage, the second signal also causing the first current to be varied. 
     
     
       7. The charge pump circuit of claim  6 , wherein the first transistor means further comprises sense means connected in series to the first and second transistors to provide the third voltage. 
     
     
       8. The charge pump circuit of claim  7 , wherein the second response means comprises a second operational amplifier having non-inverting and inverting input terminals for receiving the reference and third voltages, respectively and an output terminal for providing the second signal, the second operational amplifier varying the second signal so that the reference and third voltages are matched. 
     
     
       9. The charge pump circuit of claim  7 , wherein the sense means comprises a resistance element. 
     
     
       10. The charge pump circuit of claim  4 , wherein the first feeding means comprises a first switching means for turning on and off in response to the first input signal, so that the first signal is forwarded to the input control electrode of the third transistor and the second current is varied, when the first switching means is on. 
     
     
       11. The charge pump circuit of claim  10 , wherein the second feeding means comprises a second switching means for turning on and off in response to the second input signal, so that the second signal is forwarded to the input control electrode of the fourth transistor and the third current is varied, when the second switching means is on. 
     
     
       12. The charge pump circuit of claim  4 , wherein the first and third transistors are FETs of a first channel type and the second and fourth transistors are FETs of a second channel type. 
     
     
       13. The charge pump circuit of claim  12 , wherein the first and second channel types are P- and N-channels, respectively. 
     
     
       14. The charge pump circuit of claim  12 , wherein all of the FETs are metal oxide semiconductor transistors.