Method of manufacturing a trench gate field effect semiconductor device

Abstract

A semiconductor body ( 1 ) is provided having a first semiconductor region ( 3 ) of one conductivity type separated from a first major surface ( 5 a ) by a second semiconductor region ( 5 ) of the opposite conductivity type. A trench ( 7 ) is etched through the second semiconductor region ( 5 ) to an etch stop layer ( 4 ) provided in the region of the pn junction between the first ( 3 ) and second ( 5 ) regions, by using an etching process which enables the etching process to be stopped at the etch stop layer. A gate ( 8, 9 ) is provided within the trench ( 7 ). A source ( 12 ) separated from the first region ( 3 ) by the second region ( 5 ) is formed adjacent the trench so that a conduction channel area ( 50 ) of the second region ( 5 ) adjacent the trench provides a conduction path between the source and first regions which is controllable by the gate.

What is claimed is:  
     
       1. A method of manufacturing a semiconductor device comprising a trench gate field effect device, which method comprises: providing a semiconductor body having first and second major surfaces with a first semiconductor region of one conductivity type separated from the first major surface by a second semiconductor region of the opposite conductivity type; etching a trench through the second semiconductor region; providing a gate within the trench; forming adjacent the trench a source region separated from the first region by the second region with a conduction channel area of the second region adjacent the trench providing a conduction path between the source and first regions which is controllable by the gate, characterised by providing an etch stop layer in the region of the pn junction between the first and second regions; and etching said trench using an etching process which enables the etching process to be stopped at the etch stop layer. 
     
     
       2. A method according to claim  1 , which comprises etching said trench using an etching process which, at least as the bottom of the trench being formed by the etching process approaches, the etch stop layer etches said first and second regions selectively relative to said etch stop layer enabling etching of the trench to be stopped at said etch stop layer. 
     
     
       3. A method according to claim  2 , which comprises etching only the portion of the trench which is closest to the etch stop layer using an etching process which etches said first and second regions selectively relative to said etch stop layer. 
     
     
       4. A method according to claim  2 , which comprises etching the majority of the trench using an anisotropic etching process and etching the final portion of the trench to said etch stop layer using an isotropic etching process which etches said first and second regions selectively relative to said etch stop layer. 
     
     
       5. A method according to claim  1 , which comprises providing the first and second regions as regions of monocrystalline silicon and providing said etch stop layer as a silicon-germanium layer. 
     
     
       6. A method according to claim  2 , which comprises providing the first and second regions as regions of monocrystalline silicon and providing said etch stop layer as a silicon-germanium layer and which further comprises using potassium hydroxide to etch the first and second regions selectively with respect to said etch stop layer. 
     
     
       7. A method according to claim  5 , which comprises providing the etch stop layer as a silicon-germanium layer selected from the following group: a silicon-germanium layer containing 10 atom % of germanium and having a thickness of 40 nanometers; a silicon-germanium layer containing 20 atom % of germanium and having a thickness of less than or equal to 20 nanometers; a silicon-germanium layer containing 5 atom % of germanium and having a thickness of less than or equal to 400 nanometers; a silicon-germanium layer containing 10 atom % of germanium and having a thickness of less than or equal to 60 to 65 nanometers; a silicon-germanium layer containing 20 atom % of germanium and having a thickness of less than or equal to 30 nanometers; and a silicon-germanium layer containing 30 atom % of germanium and having a thickness of less than or equal to 20 nanometers. 
     
     
       8. A method according to claim  1 , which comprises providing the etch stop layer at the pn junction. 
     
     
       9. A method according to claim  1 , which comprises providing the etch stop layer in the first region. 
     
     
       10. A method according to claim  1  which comprises providing the first and second regions ( 3  and  5 ) and the etch stop layer ( 4 ) as epitaxial layers. 
     
     
       11. A method according to claim  1 , which comprises providing the gate by providing a gate dielectric layer on the walls of the trench and then providing a conductive gate region in the trench. 
     
     
       12. A method according to claim  1 , which comprises providing the source region as a semiconductor region of the one conductivity type.