Chip testing system

Abstract

A chip testing system using an internal signal of the chip under test to produce a blanking signal so as to avoid a conflict in the turn-around cycle between input mode and output mode. The preceding signal, posterior signal and reverse phase signal of the output enable signal of the chip under test are used to match with a testing circuit for producing a blanking signal, which is driven only when the output enable signal is at a high potential, enabling the state machine in the chip to control data reading time, so as to avoid a conflict in the turn-around cycle between input mode and output mode.

What the invention claimed is:  
     
       1. A chip testing system coupled to a chip for testing said chip's quality, said chip testing system applying an input test data to said chip in an input mode and reading an output test data in an output mode, said input and output test data having a predetermined test cycle, wherein a conflict occurs during a turn-around cycle between said input and output modes, said chip testing system comprising a testing circuit coupled to said chip to receive therefrom an output enable signal indicative of outputting said output test data and a preceding signal output prior to said output enable signal, said testing circuit generating a blanking signal responsive to input of said output enable signal and said preceding signal and supplying said blanking signal to said chip to control reading of said input test data, said blanking signal being output to delay said output mode after said input mode and delay said input mode after said output mode, thereby eliminating any effects from said conflict during said turn-around cycle. 
     
     
       2. The chip testing system of  claim 1 , wherein said testing circuit further comprises 
       (a) an align unit receiving at inputs thereof said output enable signal and said preceding signal, said align unit producing first and second output signals from said received output enable and preceding signals, said first and second output signals being synchronized with said test cycle, and  
       (b) an XOR gate having inputs thereof connected to outputs of said align unit, said XOR gate receiving said first and second output signals from said outputs of said align unit, and combining said first and second output signals to produce said blanking signal at an output thereof.  
     
     
       3. The chip testing system of  claim 1 , wherein said testing circuit comprises an XOR gate receiving said output enable signal and said preceding signal from said chip, and an align unit having an input thereof connected to an output of said XOR gate to receive an output signal from said XOR gate, and to generate said blanking signal. 
     
     
       4. The chip testing system of  claim 1 , wherein said testing circuit further includes an input for receiving a posterior signal output subsequent to said output enable signal, an d wherein said blanking signal is formed by combining an inverted version of said output enable signal, said preceding signal and said posterior signal, said blanking signal being at a high potential when both said preceding signal and said inverted version of said output enable signal are at a high potential and when both said posterior signal and said inverted version of said output enable signal are at a high potential thereat. 
     
     
       5. The chip testing system of  claim 4 , wherein said testing circuit includes a first AND gate, a second AND gate, and an OR gate, said preceding signal being applied to an input of said first AND gate, said inverted version of said output enable signal being applied to inputs of both said first and second AND gates, said posterior signal being applied to a n input of said second AND gate, said OR gate having input terminals respectively coupled to output terminals of said first AND gate and said second AND gate, said blanking signal being output from an output terminal of said OR gate. 
     
     
       6. The chip testing system of  claim 1 , wherein said testing circuit is disposed on said chip being tested. 
     
     
       7. A chip test system comprising: 
       a tester for outputting an input test data in an input mode and reading an output test data in an output mode, wherein said input and output test data have a predetermined test cycle;  
       a chip coupled to said tester for reading said input data in said input mode and outputting said output data in said output mode; and  
       a testing circuit coupled to said chip for generating a blanking signal responsive to a plurality of signals generated by said chip to control reading of said input test data;  
       wherein said blanking signal is output to delay said output mode after said input mode and to delay said input mode after said output mode, thus eliminating a conflict that occurs during a turn-around cycle between said input and output modes.  
     
     
       8. The chip testing system of  claim 7 , wherein said signals comprise an output enable signal indicative of outputting said output test data and a preceding signal output prior to said output enable signal. 
     
     
       9. The chip testing system of  claim 8 , wherein said signals further comprise a posterior signal output subsequent to said output enable signal, and wherein said blanking signal is formed by combining an inverted version of said output enable signal, said preceding signal and said posterior signal, said blanking signal being at a high potential when both said preceding signal and said inverted version of said output enable signal are at a high potential and when both said posterior signal and said inverted version of said output enable signal are at a high potential thereat. 
     
     
       10. The chip testing system of  claim 9 , wherein said testing circuit includes a first AND gate, a second AND gate and an OR gate, said preceding signal being applied to an input of said first AND gate, said inversion version of said output enable signal being applied to inputs of both said first and second AND gates, said posterior signal being applied to an inputs of said second AND gate, said OR gate having input terminals respectively coupled to output terminals of said first AND gate and said second AND gate, said blanking signal being output from an output terminal of said OR gate. 
     
     
       11. The chip testing system of  claim 8 , wherein said testing circuit further comprises: 
       (a) an align unit receiving at inputs thereof said output enable signal and said preceding signal, said align unit producing first and second output signals from said received output enable and preceding signals, said first and second output signals being synchronized with said predetermined test cycle, and  
       (b) an XOR gate having inputs thereof connected to outputs of said align unit, said XOR gate receiving said first and second output signals from said outputs of said align unit, and combining said first and second output signals to produce said blanking signal at an output thereof.  
     
     
       12. The chip testing system of  claim 7 , wherein said testing circuit comprises an XOR gate receiving said output enable signal and said preceding signal from said chip, and an align unit having an input thereof connected to an output of said XOR gate to receive an output signal from said XOR gate, and to generate said blanking signal. 
     
     
       13. The chip testing system if  claim 7 , wherein said testing circuit is disposed on said chip being tested.