Array substrate for use in liquid crystal display device and method of manufacturing the same

Abstract

A 4-mask method of manufacturing an array substrate. First and second masks form a gate line, a gate pad, a data line and a data pad. The data line has a protrusion near a crossing of the gate and data lines. A third mask forms a transparent electrode layer, a source electrode, a drain electrode, a pixel electrode, and exposes channel area. The transparent electrode layer has a similar shape as the data line and the data pad, but a smaller area than the data line and a greater area than the data pad. A second insulating layer is formed over the structure. A fourth mask patterns the second insulating layer to cover the gate line and the gate pad, the first and second insulating layer are patterned to form a gate pad contact hole, and the first insulating layer between the data line and the pixel electrode is patterned.

What is claimed is:  
     
       1. A method of manufacturing an array substrate for use in a thin film transistor liquid crystal display device, comprising: 
       depositing sequentially a first opaque conductive metal layer and a first transparent conductive metal layer on a substrate;  
       patterning the first opaque conductive metal layer and the first transparent conductive metal layer using a first mask to form a gate line and a gate pad, the gate line connected with the gate pad at an end portion thereof;  
       depositing sequentially a first insulating layer, an intrinsic semiconductor layer, a doped semiconductor layer and a second opaque conductive metal layer on the exposed surface of the substrate while covering the gate line and the gate pad;  
       patterning simultaneously the intrinsic semiconductor layer, the doped semiconductor layer and the second opaque conductive layer using a second mask to form a data line and a data pad, the data line perpendicular to the gate line and connected with the data pad at an end portion thereof and having a protruding portion at a cross portion of the gate and data line, the protruding portion extending toward a longitudinal direction of the gate line;  
       depositing a second transparent conductive metal layer over the whole surface of the substrate while covering the data line and the data pad;  
       patterning simultaneously the seconding transparent conductive metal layer, the second opaque conductive metal layer and the doped semiconductor layer using a third mask to form a transparent electrode layer, a source electrode, a drain electrode and a pixel electrode and to expose a channel area of the intrinsic semiconductor layer, the transparent electrode layer formed on the data line and the data pad and having the similar shape to the data line and the data pad and having a greater area than the data line and a smaller area than the data pad, the source and drain electrodes spaced apart from each other, the pixel electrode extending from the drain electrode;  
       forming a second insulating layer over the whole surface of the substrate while covering the transparent electrode layer, the source and drain electrodes and the pixel electrode; and  
       patterning the second insulating layer to cover the gate line and the gate pad, patterning simultaneously portions of the first and second insulating layer on the gate pad to form a gate pad contact hole, and patterning portions of the first insulating layer between the data line and the pixel electrode, using a fourth mask.  
     
     
       2. The method of  claim 1 , wherein the first and second opaque conductive metal layer is made of one of aluminum, aluminum alloy, Cr, Mo, W and Ta. 
     
     
       3. The method of  claim 1 , wherein the first and second transparent conductive metal layer is made of one of indium tin oxide and indium zinc oxide. 
     
     
       4. The method of  claim 1 , wherein the first insulating layer is made of one of SiO 2  and SiNx, and the second insulating layer is made of one of SiO 2 , SiNx, benzocyclobutene (BCB) and acrylic-based resin. 
     
     
       5. The method of  claim 1 , wherein the first insulating layer includes silicon atoms. 
     
     
       6. The method of  claim 1 , wherein the second insulating layer includes silicon atoms. 
     
     
       7. The method of  claim 1 , wherein the second insulating layer includes benzocyclobutene. 
     
     
       8. The method of  claim 1 , wherein the second transparent conductive layer includes indium atoms. 
     
     
       9. The method of  claim 1 , wherein the first opaque conductive metal layer includes aluminum atoms. 
     
     
       10. An array substrate fabricated by a method comprising the steps of: 
       (a) depositing a first metallic conductor on an exposed surface of a substrate;  
       (b) patterning said first metallic conductor using a first mask to produce a gate line and a gate pad that are connected together;  
       (c) depositing an insulating layer, an intrinsic semiconductor layer, a doped semiconductor layer, and a second metallic layer over a surface that results from step (a);  
       (d) patterning said intrinsic semiconductor layer, said doped semiconductor layer, and said second metallic layer using a second mask so as to form a data line and a data pad that are interconnected, wherein said data line crosses said gate line, and wherein said data line includes a protruding portion near said crossing and that extends along said gate line;  
       (e) depositing a blanketing conductive layer over a surface that results from step (d):  
       (f) patterning said blanketing conductive layer deposited in step (d), and said second metallic layer and said doped semiconductor layer deposited in step (c) using a third mask so as to form an electrode layer, a source electrode, a drain electrode, a pixel electrode, and an exposed channel area of the intrinsic semiconductor layer;  
       (g) depositing a passivation layer over a surface that results from step (f); and  
       (h) patterning said passivation layer and said insulating layer to form a gate pad contact hole.  
     
     
       11. An array substrate fabricated according to  claim 10 , wherein the step of depositing the first metallic conductor includes steps of depositing both a base metal layer and an overlay layer such that said first metallic conductor has a dual layer structure. 
     
     
       12. An array substrate fabricated according to  claim 11 , wherein the step of depositing said base metal layer deposits at least one metal from a group comprised of aluminum or an aluminum alloy. 
     
     
       13. An array substrate fabricated according to  claim 11 , wherein the step of depositing said overlay layer deposits a material from a group comprised of indium tin oxide and indium zinc oxide. 
     
     
       14. An array substrate fabricated according to  claim 11 , wherein step (d) produces said data line such that said data line is perpendicular to said gate line. 
     
     
       15. An array substrate fabricated according to  claim 11 , wherein step (e) is performed by depositing said blanketing conductive layer so as to form a transparent layer. 
     
     
       16. An array substrate fabricated according to  claim 11 , wherein step (e) is performed by depositing a material from a group comprised of indium tin oxide and indium zinc oxide. 
     
     
       17. An array substrate fabricated according to  claim 15 , wherein step (f) produces a transparent electrode layer. 
     
     
       18. An array substrate fabricated according to  claim 11 , wherein step (f) produces a transparent pixel electrode. 
     
     
       19. An array substrate fabricated according to  claim 11 , wherein step (f) produces an electrode layer over said data line. 
     
     
       20. An array substrate fabricated according to  claim 19 , wherein said electrode layer over said data line has a similar shape as said data line, but has a smaller area. 
     
     
       21. An array substrate fabricated according to  claim 11 , wherein step (f) produces an electrode layer over said data pad. 
     
     
       22. An array substrate fabricated according to  claim 21 , wherein said electrode layer over said data pad has a similar shape as said data pad, but has a larger area. 
     
     
       23. An array substrate fabricated according to  claim 11 , wherein step (h) leaves said passivation material over said gate line and over said data pad. 
     
     
       24. An array substrate fabricated according to  claim 11 , wherein step (h) removes insulating material between said data line and said pixel electrode. 
     
     
       25. An array substrate fabricated according to  claim 11 , wherein step (h) leaves said passivation material over said source electrode and over said drain electrode.