Low-current sample rate converter

Abstract

A low power sample rate converter adapted for use with a telecommunications system transceiver. The sample rate converter includes a first circuit that provides an input signal characterized by a first sample rate and a delayed version of the input signal. A second circuit periodically multiplies, at a second sample rate, samples in the input signal by a first predetermined coefficient in accordance with a predetermined transfer function and provides a first signal in response thereto. A third circuit periodically multiplies, at the second sample rate, samples in the delayed version of the input signal by a second predetermined coefficient in accordance with the predetermined transfer function and provides a second signal in response thereto. A fourth circuit combines the first signal and second signal providing a rate-converted version of the input signal as an output signal in response thereto. In a specific embodiment, the delayed version of the input signal is delayed by one sample with respect to the input signal. The sample rate converter further includes a counter that is clocked by a first periodic signal. The first periodic signal has a frequency related to the first sample rate by a predetermined fraction. The counter is cleared by a second periodic signal having a second frequency equivalent to the first sample rate. The counter produces a counter output at the first frequency. In the preferred embodiment, the predetermined fraction is ⅓ and the first predetermined coefficient is equivalent to the sum of 1 and the counter output. The second predetermined coefficient is equivalent to the difference of 2 and the counter output. The fourth circuit includes an adder for adding the first signal and the second signal and providing the output signal in response thereto. The predetermined transfer function is represented by the following coefficient sequence: [1 2 3 2 1].

What is claimed is:  
     
       1. A low power sample rate converter comprising: 
       first means for providing an input signal characterized by a first sample rate and for providing a delayed version of said input signal;  
       second means for periodically multiplying a first sample in said input signal by a first predetermined coefficient at a second sample rate and in accordance with a predetermined transfer function and providing a first signal in response thereto;  
       third means for periodically multiplying a second sample in said delayed version of said input signal by a second predetermined coefficient at said second sample rate and in accordance with said predetermined transfer function and providing a second signal in response thereto; and  
       fourth means for combining said first signal and said second signal and providing a rate-converted version of said input signal as an output signal in response thereto.  
     
     
       2. The invention of  claim 1  wherein said delayed version of said input signal is delayed by one sample with respect to said input signal. 
     
     
       3. The invention of  claim 2  further including a counter. 
     
     
       4. The invention of  claim 3  wherein said counter is clocked by a first periodic signal having a first frequency related to said first sample rate by a predetermined fraction and cleared by a second periodic signal having a second frequency equivalent to said first sample rate, said counter producing a counter output at said first frequency. 
     
     
       5. The invention of  claim 4  wherein said predetermined fraction is ⅓. 
     
     
       6. The invention of  claim 4  wherein said first predetermined coefficient is equivalent to the sum of 1 and said counter output. 
     
     
       7. The invention of  claim 6  wherein said second predetermined coefficient is equivalent to the difference of two and said counter output. 
     
     
       8. The invention of  claim 7  wherein said fourth means includes an adder for adding said first signal and said second signal and providing said output signal in response thereto. 
     
     
       9. The invention of  claim 1  wherein said predetermined transfer function is: 
       
         
           (1+z −1 +z −2 ) 2 .  
         
       
     
     
       10. The invention of  claim 1  wherein said predetermined transfer function is represented by the following coefficient sequence: [1 2 3 2 1]. 
     
     
       11. A low power sample rate converter comprising: 
       clock generation means for generating a first clock signal;  
       input means for receiving an input signal characterized by a first sample rate;  
       enable means for comparing said first clock signal to said input signal and providing an enable signal when said input signal is stable near an edge of a clock pulse in said first clock signal in response thereto;  
       sample rate conversion means for sampling said input signal at a second sample rate and providing a rate-converted signal in response to said enable signal; and  
       filter means for selectively multiplying said rate-converted signal by a predetermined coefficient and providing a sample rate converter output signal in response thereto.  
     
     
       12. The invention of  claim 11  wherein said edge is a rising edge occurring in said first clock signal. 
     
     
       13. The invention of  claim 11  wherein said filter means includes means for providing a count. 
     
     
       14. The invention of  claim 13  wherein said means for providing a count includes a counter. 
     
     
       15. The invention of  claim 14  wherein said counter includes means for receiving said first clock signal as an input and incrementing a count for each clock pulse received via said first clock signal, said count reset every pulse from a second clock having a frequency approximately equal to said first sample rate. 
     
     
       16. The invention of  claim 15  wherein said filter means further includes means for inserting a time delay, said means for inserting a time delay clocked by said first clock signal. 
     
     
       17. The invention of  claim 16  wherein said means for inserting a time delay is a register. 
     
     
       18. The invention of  claim 17  wherein said register includes one or more flip-flops. 
     
     
       19. The invention of  claim 16  wherein an input of said register is connected to an output of said counter, said register outputting said count in response to a high pulse in said first clock signal when said count is provided at said input by said counter. 
     
     
       20. The invention of  claim 16  wherein said filter means further includes second means for inserting a time delay, said second means for inserting a time delay connected to an output of said first means for inserting a time delay, said second means for inserting a time delay clocked at said second sample rate. 
     
     
       21. The invention of  claim 13  wherein said filter means further includes means for simulating zero insertion in said rate-converted signal without inserting zeros within said rate-converted signal. 
     
     
       22. The invention of  claim 21  wherein said filter means further includes a means for selectively adding a first predetermined constant to said count and/or subtracting a second predetermined constant from said count, and providing a first output signal and/or a second output signal in response thereto, respectively. 
     
     
       23. The invention of  claim 22  wherein said means for selectively adding includes an adder and a subtractor, said count provided to a first input of said adder and to a first input of said subtractor. 
     
     
       24. The invention of  claim 23  wherein a second input of said adder is connected to a voltage source representative of said first predetermined constant, an output of said adder providing said second output signal. 
     
     
       25. The invention of  claim 24  wherein said first predetermined constant is 1. 
     
     
       26. The invention of  claim 23  wherein a second input of said subtractor is connected to a voltage source representative of said second predetermined constant, an output of said subtractor providing said first output signal. 
     
     
       27. The invention of  claim 26  wherein said second predetermined constant is 2. 
     
     
       28. The invention of  claim 22  wherein said filter means further includes a first multiplier and a second multiplier, said first multiplier receiving said first output signal as a first input, and said second multiplier receiving said second output signal as a first input. 
     
     
       29. The invention of  claim 28  wherein a second input of said first multiplier receives said rate-converted signal. 
     
     
       30. The invention of  claim 29  wherein a second input of said second multiplier receives a delayed version of said rate-converted signal. 
     
     
       31. The invention of  claim 30  wherein said delayed version of said rate-converted signal is delayed by an amount equivalent to a time difference between successive samples of a signal characterized by said first sample rate. 
     
     
       32. The invention of  claim 31  wherein outputs of said first multiplier and said second multiplier are input to a second adder, said second adder outputting said sample rate converter output signal. 
     
     
       33. The invention of  claim 1  wherein said predetermined filter coefficient is to one of the following numbers: 1 2 3. 
     
     
       34. A low power sample rate converter comprising: 
       a first input register clocked at a first rate;  
       a second register clocked at said first rate and connected in series to said first input register;  
       a counter clocked at a second rate and cleared at said first rate;  
       a first set of reclocking registers clocked at a second rate and connected to said first input register, said second register, and said counter and providing a first output signal, second output signal, and third output signal, respectively, in response thereto;  
       a second set of reclocking registers clocked at a third rate and connected to said first set of reclocking registers and providing a first output, second output, and third output corresponding to said first output signal, said second output signal, and said third output signal, respectively;  
       an adder circuit connected at an output of said counter, said adder circuit including a first adder and a second adder for adding a first predetermined value and a second predetermined value to said output of said counter and providing a first coefficient output and a second coefficient output, respectively;  
       a multiplier circuit having a first multiplier and a second multiplier connected to said first output and said second output and to said first coefficient output and said second coefficient output, respectively, and providing a first multiplier output and a second multiplier output; and  
       an output adder connected to said first multiplier output and said second multiplier output and providing a sample rate converter output.  
     
     
       35. A low power sample rate converter comprising: 
       first means for providing an input signal characterized by a first sample rate and for providing a delayed version of said input signal;  
       second means for periodically multiplying a first sample in said input signal by a first predetermined coefficient at a second sample rate and providing a first signal in response thereto;  
       third means for periodically multiplying a second sample in said delayed version of said input signal by a second predetermined coefficient at said second sample rate and providing a second signal in response thereto; and  
       fourth means responsive to said second signal for providing a rate-converted version of said input signal.  
     
     
       36. A method for effecting sample rate conversion comprising the steps of: 
       providing an input signal characterized by a first sample rate and for providing a delayed version of said input signal;  
       periodically multiplying a first sample in said input signal by a first predetermined coefficient at a second sample rate and in accordance with a predetermined transfer function and providing a first signal in response thereto;  
       periodically multiplying a second sample in said delayed version of said input signal by a second predetermined coefficient at said second sample rate and in accordance with said predetermined transfer function and providing a second signal in response thereto; and  
       combining said first signal and said second signal and providing a rate-converted version of said input signal as an output signal in response thereto.