US6350651B1ExpiredUtility

Method for making flash memory with UV opaque passivation layer

38
Assignee: INTEL CORPPriority: Jun 10, 1999Filed: Jun 10, 1999Granted: Feb 26, 2002
Est. expiryJun 10, 2019(expired)· nominal 20-yr term from priority
H10W 42/20H10D 64/035
38
PatentIndex Score
10
Cited by
2
References
4
Claims

Abstract

A method for making a flash memory having a passivation layer that is not transparent to ultraviolet light. The method comprises forming a semiconductor substrate that includes a flash memory cell having a floating gate, then forming a conductive layer on the substrate. Process induced charge that has accumulated on the flash cell floating gate is then neutralized and a passivation layer, which is not transparent to ultraviolet light, is formed on the conductive layer.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
       1. A method for making a flash memory comprising: 
       forming a semiconductor substrate that includes a flash memory cell that has a floating gate;  
       forming a conductive layer on the substrate; then  
       neutralizing process induced charge that has accumulated on the flash memory cell's floating gate by exposing the substrate to ultraviolet light; and then  
       forming on the conductive layer a passivation layer that comprises a barrier layer that comprises a silicon nitride layer and a stress reduction layer that comprises a polyimide layer.  
     
     
       2. The method of  claim 1  wherein the flash memory cell's floating gate has a gate length that is less than about 0.5 microns. 
     
     
       3. The method of  claim 2  wherein the flash memory includes a final metal interconnect and wherein the conductive layer forms the final metal interconnect for the flash memory, upon which is formed the passivation layer. 
     
     
       4. A method for making a flash memory that includes a final metal interconnect comprising: 
       forming a semiconductor substrate that includes a flash memory cell that has a floating gate that has a gate length that is less than about 0.5 microns;  
       forming a conductive layer on the substrate that forms the final metal interconnect for the flash memory; then  
       exposing the flash memory cell's floating gate to ultraviolet light; and then  
       forming on the conductive layer a passivation layer that comprises a silicon nitride layer and a polyimide layer.

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