Method for manufacturing a thin film transistor for protecting source and drain metal lines

Abstract

A method for manufacturing a thin film transistor includes the step of forming a protective layer for protecting source and drain metal lines during a cleaning process. The protective layer is preferably made of silicon nitride and preferably has a thickness of less than about 2000 angstroms.

What is claimed is:  
     
       1. A method for manufacturing a thin film transistor, the method comprising: 
       forming source and drain metal lines on an insulating substrate;  
       forming a first protective layer covering the source and drain metal lines;  
       sequentially depositing a buffer layer and a semiconductor layer on the first protective layer;  
       forming an active layer by patterning and etching the semiconductor layer;  
       etching the buffer layer using the active layer as a mask;  
       performing a cleaning process before depositing a gate insulating layer on an exposed surface of the substrate;  
       forming the gate insulating layer and a gate electrode on the active layer;  
       forming source and drain regions in the active layer by doping the active layer with impurities using the gate insulating layer as a mask;  
       forming a second protective layer covering the exposed entire surface of the substrate including the gate electrode;  
       forming contact holes in the first and second protective layers, thereby exposing the source and drain metal lines and the source and drain regions; and  
       forming a first metal line connecting the source metal line and the source region, and a second metal connecting the drain metal line and the drain region.  
     
     
       2. The method according to  claim 1 , wherein the cleaning process is performed with an HF cleaning solution. 
     
     
       3. The method according to  claim 1 , further comprising the step of crystallizing the semiconductor layer. 
     
     
       4. The method according to  claim 3 , further comprising the step of activating the active layer after doping the active layer with the impurities. 
     
     
       5. The method according to  claim 1 , further comprising the step of activating the active layer after doping the active layer with the impurities. 
     
     
       6. The method according to  claim 1 , wherein the first protective layer and the buffer layer are made of different materials. 
     
     
       7. The method according to  claim 6 , wherein the first protective layer is made of silicon nitride and the buffer layer is made of silicon oxide. 
     
     
       8. The method according to  claim 1 , wherein the source metal line has a double-layered laminate structure including a first source metal line and a second source metal line and wherein the drain metal line has a double-layered laminate structure including a first rain metal line and a second drain metal line. 
     
     
       9. The method according to  claim 8 , wherein said first source metal line is made from at least one of Al, AlMo, AlTa, and AiNd, wherein said second source metal line is made from at least one of Mo, Cr, Ni, Ti, W, MoW, Ta, Al, Ta, and AlNd, wherein said first drain metal line is made from at least one of Al, AlMo, AlTa, and AlNd, and wherein said second drain metal line is made from at least one of Mo, Cr, Ni, Ti, W, MoW, Ta, Al, Ta, and AlNd. 
     
     
       10. A method for manufacturing a thin film transistor comprising the steps of: 
       forming source and drain metal lines on an insulating substrate;  
       forming a first protective layer covering the source and drain metal lines;  
       sequentially depositing a buffer layer and a semiconductor layer on the first protective layer;  
       forming an active layer by patterning and etching the semiconductor layer;  
       etching the buffer layer using the active layer as a mask;  
       forming source and drain regions in the active layer by selectively doping the active layer with impurities;  
       performing a cleaning process before depositing a gate insulating layer on an exposed entire surface of the substrate;  
       forming the gate insulating layer and a gate electrode on the active layer;  
       forming a second protective layer covering the exposed surface of the substrate including the gate electrode;  
       forming contact holes in the first and second protective layers so that the source and drain metal lines and the source and drain regions are exposed; and  
       forming a first metal line connecting the source metal line and the source region, and a second metal line connecting the drain metal line and the drain region.  
     
     
       11. The method according to  claim 10 , wherein the cleaning process is performed with an HF cleaning solution. 
     
     
       12. The method according to  claim 10 , further comprising the step of crystallizing the semiconductor layer. 
     
     
       13. The method according to  claim 12 , further comprising the step of activating the active layer after doping the active layer with the impurities. 
     
     
       14. The method according to  claim 10  further comprising the step of activating the active layer after doping the active layer with the impurities. 
     
     
       15. The method according to  claim 10 , further comprising the step of performing a laser annealing process for simultaneously activating and crystallizing the active layer, after doping the active layer with the impurities. 
     
     
       16. The method according to  claim 10 , wherein the first protective layer and the buffer layer are made of different materials. 
     
     
       17. The method according to  claim 16 , wherein the first protective layer is made of silicon nitride and the buffer layer is made of silicon oxide. 
     
     
       18. The method according to  claim 10 , wherein the source metal line has a double-layered laminate structure including a first source metal line and a second source metal line and wherein the drain metal line has a double-layered laminate structure including a first drain metal line and a second drain metal line. 
     
     
       19. The method according to  claim 18 , wherein said first source metal line is made from at least one of Al, AlMo, AlTa, and AlNd, wherein said second source metal line is made from at least one of Mo, Cr, Ni, Ti, W, MoW, Ta, Al, Ta, and AlNd, wherein said first drain metal line is made from at least one of Al, AlMo, AlTa, and AlNd, and wherein said second drain metal line is made from at least one of Mo, Cr, Ni, Ti, W, MoW, Ta, Al, Ta, and AlNd. 
     
     
       20. A method for manufacturing a thin film transistor comprising the steps of: 
       forming source and drain metal lines of an insulating substrate; and  
       forming a first protective layer covering the source and drain metal lines prior to cleaning the substrate and forming a gate electrode.  
     
     
       21. The method according to  claim 20 , further comprising the step of sequentially depositing a buffer layer and the semiconductor layer on the first protective layer. 
     
     
       22. The method according to  claim 21 , further comprising the step of forming an active layer by patterning and etching the semiconductor layer. 
     
     
       23. The method according to  claim 22 , further comprising the step of crystallizing the semiconductor layer. 
     
     
       24. The method according to  claim 23 , further comprising the step of activating the active layer after doping the active layer with the impurities. 
     
     
       25. The method according to  claim 22 , further comprising the step of activating the active layer after doping the active layer with the impurities. 
     
     
       26. The method according to  claim 22 , further comprising the step of etching the buffer layer using the active layer as a mask. 
     
     
       27. The method according to  claim 26 , further comprising the step of performing a cleaning process before depositing a gate insulating layer on an exposed surface of the substrate. 
     
     
       28. The method according to  claim 27 , wherein the step of performing a cleaning process further includes the step of using an HF cleaning solution. 
     
     
       29. The method according to  claim 27 , further comprising the step of forming a gate insulating layer and a gate electrode on the active layer. 
     
     
       30. The method according to  claim 29 , further comprising the step of forming source and drain regions in the active layer by doping the active layer with impurities using the gate insulating layer as a mask. 
     
     
       31. The method according to  claim 30 , further comprising the step of forming a second protective layer covering the exposed entire surface of the substrate including the gate electrode. 
     
     
       32. The method according to  claim 21 , further comprising the step of forming contact holes in the first and second protective layers, thereby exposing the source and drain metal lines and the source and drain regions. 
     
     
       33. The method according to  claim 32 , further comprising the step of forming a first metal line connecting the source metal line and the source region, and a second metal line connecting the drain metal line and the drain region. 
     
     
       34. The method according to  claim 26 , further comprising the step of forming source and drain regions in the active layer by selectively doping the active layer with impurities. 
     
     
       35. The method according to  claim 34 , further comprising the step of performing a cleaning process before depositing a gate insulating layer on an exposed surface of the substrate. 
     
     
       36. The method according to  claim 35 , further comprising the step of forming a gate insulating layer and a gate electrode on the active layer. 
     
     
       37. The method according to  claim 36 , further comprising the step of forming a second protective layer covering the exposed entire surface of the substrate including the gate electrode. 
     
     
       38. The method according to  claim 37 , further comprising the step of forming contact holes in the first and second protective layers, thereby exposing the source and drain metal lines and the source and drain regions. 
     
     
       39. The method according to  claim 38 , further comprising the step of forming a first metal line connecting the source metal line and the source region, and a second metal line connecting the drain metal line and the drain region. 
     
     
       40. The method according to  claim 34 , further comprising the step of performing a laser annealing process for simultaneously activating and crystallizing the active layer, after doping the active layer with the impurities. 
     
     
       41. The method according to  claim 20 , wherein the first protective layer and the buffer layer are made of different materials. 
     
     
       42. The method according to  claim 41 , wherein the first protective layer is made of silicon nitride and the buffer layer is made of silicon oxide. 
     
     
       43. The method according to  claim 20 , wherein the source metal line has a double-layered laminate structure including a first source metal line and a second source metal line and wherein the drain metal line has a double-layered laminate structure including a first drain metal line and a second drain metal line. 
     
     
       44. The method according to  claim 43 , wherein said first source metal line is made from at least one of Al, AlMo, AlTa, and AlNd, wherein said second source metal line is made from at least one of Mo, Cr, Ni, Ti, W, MoW, Ta, Al, Ta, and AlNd, wherein said first drain metal line is made from at least one of Al, AlMo, AlTa, and AlNd, and wherein said second drain metal line is made from at least one of Mo, Cr, Ni, Ti, W, MoW, Ta, Al, Ta, and AlNd.