Static random access memory (SRAM)

Abstract

According to one embodiment, an asynchronous static random access memory (SRAM) circuit ( 100 ) can provide reduced power consumption and high-speed access. An SRAM circuit ( 100 ) may include address registers ( 122 and 128 ) that can store a write address from one write operation and output the stored write address during a subsequent write operation. A data register ( 138 ) may also be included that can store write data from one write operation and output the stored write data during a subsequent write operation. Memory cells of a memory cell array ( 102 ) may be selected according to a pulse word signal PW. A pulse word signal PW can be generated in response to transitions in an address and transitions in a write enable signal /WE. Hit address comparators ( 220 ) within address registers ( 122 and 128 ) in combination with a hit AND gate ( 136 ) can activate a HIT ALL signal when a stored write address matches an applied read address. When the HIT ALL signal is activated, an output circuit ( 118 ) can output stored write data instead of an output from a sense amplifier circuit ( 116 ).

What is claimed is:  
     
       1. A static random access memory (SRAM) circuit, comprising: 
       a plurality of SRAM cells that can be selected according to an internal pulse signal that is not generated in response to an external periodic timing signal; and  
       an address register circuit that can store a write address value during one write operation and output the stored write address during a subsequent write operation.  
     
     
       2. The SRAM circuit of  claim 1 , further including: 
       a data register circuit that can store write data during one write operation and output the stored write data during a subsequent write operation.  
     
     
       3. The SRAM circuit of  claim 1 , further including: 
       the SRAM cells are selected according to a n applied address; and  
       an internal pulse generator provides the internal pulse signal in response to transitions in the applied address.  
     
     
       4. The SRAM circuit of  claim 3 , wherein : 
       the internal pulse generator provides the internal pulse signal in response to transitions in a write enable signal when the applied address remains the same.  
     
     
       5. The SRAM circuit of  claim 1 , further including: 
       the SRAM cells are selected according to an applied address and include rows of SRAM cells each commonly coupled to a word line;  
       an X-address decoder that generates X-select signals corresponding to particular combinations of at least a portion of the applied address; and  
       a word line is selected in response to the internal pulse signal and at least one X-select signal.  
     
     
       6. The SRAM circuit of  claim 1 , further including: 
       the SRAM cells are selected according to an applied address and include columns of SRAM cells each commonly coupled to at least one digit line;  
       a Y-address decoder that generates Y-select signals corresponding to particular combinations of at least a portion of the applied address; and  
       a column switch circuit that selects at least one digit line in response to the internal pulse signal and at least one Y-select signal.  
     
     
       7. The SRAM circuit of  claim 1 , further including: 
       the SRAM cells are selected according to an applied address; and  
       an address compare circuit that activates a hit signal when an applied address value matches the address values stored in the address register circuit.  
     
     
       8. The SRAM circuit of  claim 7 , further including: 
       a data register circuit that can store write data during one write operation and output the stored write data during a subsequent write operation; and  
       an output circuit that provides a memory cell value as an output when the hit signal is inactive and provides the stored write data as an output when the hit signal is active.  
     
     
       9. The SRAM circuit of  claim 1 , wherein: 
       the SRAM cells include two driver transistors that drive complementary nodes to different potentials and two access transistors that couple the complementary nodes to a digit line pair.  
     
     
       10. The SRAM circuit of  claim 9 , wherein: 
       the SRAM cells further include two load devices coupled between the complementary nodes and a predetermined potential.  
     
     
       11. A static random access memory (SRAM) circuit, comprising: 
       a plurality of address registers that store a write address value in one write operation and output the stored write address value in a subsequent write operation, each address register includes a first address latch in series with a second address latch;  
       a control circuit that generates an internal write enable signal in response to an external write enable signal; and  
       the first address latch is placed in a through state and the second address latch is placed in a latching state when the internal write enable signal has a first value, and the first address latch is placed in the latching state and the second address latch is placed in the through state when the internal write enable signal has a second value.  
     
     
       12. The SRAM circuit of  claim 11 , further including: 
       a compare circuit that compares the stored write address value with an applied read address value and generates a hit indication when the stored write address value matches the applied read address value.  
     
     
       13. The SRAM circuit of  claim 11 , further including: 
       at least one data register that stores a write data value in one write operation and outputs the stored write data value in a subsequent write operation.