Microcode scalable processor

Abstract

A processing system in accordance with the present invention is disclosed. The processing system comprises a processor and a microcode sequencer coupled to the processor. The microcode sequencer includes a plurality of modules. Each of the modules enables a specific function based upon a selection signal from the processor. A system and method in accordance with the present invention provides for many advantages over conventional systems. First of all, there is an efficient register bank and the hardware is smaller and more efficient than a DSP. Finally, since it is possible to program macro instructions for different applications, it is more flexible than DSP systems. It also is smaller, has a lower gate count and is faster to market because it is software programmable. Unlike RISC or coprocessor type systems, only a single assembler is needed to handle DSP and multimedia instructions. In addition, a large cache memory is not required while having a higher code density for a particular application. Finally, it requires a smaller register file through the general purpose processor than a media processor, and thus context switching is faster. It does not have a big data path as a media processor. It also has higher code density and it is easier to program than a media processor application. Accordingly, a system and method in accordance with the present invention provides significant utility over existing conventional systems.

What is claimed is:  
     
       1. A processing system for processing multimedia instructions comprising: 
       a processor; and  
       a microcode sequencer coupled to the processor; the microcode sequencer including a plurality of modules, each of the modules enabling a specific function based upon a selection signal from the processor wherein one of the plurality of modules comprises a discrete cosine transform (DCT) subroutine.  
     
     
       2. The system of  claim 1  in which the microcode sequencer comprises a SRAM base and a DSP engine to handle DSP/media by microcode-like instruction stream. 
     
     
       3. The system of  claim 1  wherein the processor includes a decoder, the decoder providing the selection based upon the type of instruction provided to the processor. 
     
     
       4. The system of  claim 2  wherein the processor includes a decoder, the decoder providing the selection based system on entry point of the microcode entrance or subroutine entrance. 
     
     
       5. The system of  claim 3  in which a bit within the decoder is set to enable the selection signal and enable locking of the DSP/media engine. 
     
     
       6. The system of  claim 1  in which the processor includes: 
       a decode buffer for receiving instructions; and  
       a decoder coupled to the decode buffer and the microcode sequencer for determining the type of instruction received by the decode buffer; the decoder for enabling the selection signal to select the specific function of the microcode sequencer based upon the type of instruction.  
     
     
       7. The system of  claim 6  in which the decoder includes: 
       a multiplexer which is enabled by the selection signal and also receives a macro instruction that maps an entry address to a microcode engine within the microsequencer.  
     
     
       8. The system of  claim 7  wherein the microcode engine comprises a RAM/ROM. 
     
     
       9. The system of  claim 1  wherein the plurality of modules comprises a plurality of programmable subroutines. 
     
     
       10. The system of  claim 9  in which the plurality of programmable subroutines comprise a fast fourier transform (FFT) subroutine and a finite input response (FIR) subroutine. 
     
     
       11. The system of  claim 10  in which the microcode sequencer includes: 
       a microcode engine for receiving the selection signal and providing the specific function;  
       a microcode decoder means for decoding the instructions;  
       a hardware mechanism for receiving the decoded instructions and for providing one of the specific functions.  
     
     
       12. A processing system for processing multimedia instructions comprising: 
       a microcode sequencer; the microcode sequencer including a plurality of modules, each of the modules enabling a specific function wherein one of the plurality of modules comprises a discrete cosine transform (DCT) subroutine; and  
       a processor coupled to the microcode sequencer, the processor including a decode buffer for receiving instructions; and a decoder coupled to the decode buffer and the microcode sequencer for determining the type of instruction received by the decode buffer; the decoder for enabling a selection signal to select the specific function of the microcode sequencer based upon the type of instruction.  
     
     
       13. The system of  claim 12  wherein the processor includes a decoder, the decoder providing the selection based upon the type of instruction provided to the processor. 
     
     
       14. The system of  claim 12  in which a bit within the decoder is set to enable the selection signal. 
     
     
       15. The system of  claim 12  in which the decoder includes: 
       a multiplexer which is enabled by the selection signal and also receives a macro instruction that maps an entry address to a microcode engine within the microsequencer.  
     
     
       16. The system of  claim 15  wherein the microcode engine comprises a RAM/ROM. 
     
     
       17. The system of  claim 12  wherein the plurality of modules comprises a plurality of programmable subroutines. 
     
     
       18. The system of  claim 17  in which the plurality of programmable subroutines comprise a fast fourier transform (FFT) subroutine and a finite input response (FIR) subroutine. 
     
     
       19. The system of  claim 18  in which the microcode sequencer includes: 
       a microcode engine for receiving the selection signal and providing the specific function;  
       a microcode decoder means for decoding the instructions; and  
       a hardware mechanism for receiving the decoded instructions and for providing one of the specific functions.  
     
     
       20. A processing system for processing multimedia instructions comprising: 
       a microcode sequencer; the microcode sequencer including a plurality of modules, each of the modules enabling a specific function wherein one of the plurality of modules comprises a discrete cosine transform (DCT) subroutine, the microcode sequencer including a microcode engine for receiving the selection signal and providing the specific function; a microcode decoder means for decoding the instructions; and a hardware mechanism for receiving the decoded instructions and for providing one of the specific functions; and  
       a processor coupled to the microcode sequencer, the processor including a decode buffer for receiving instructions; and a decoder coupled to the decode buffer and the microcode sequencer for determining the type of instruction received by the decode buffer; the decoder for enabling a selection signal to select the specific function of the microcode sequencer based upon the type of instruction, the decoder including a multiplexer which is enabled by the selection signal and also receives a macro instruction that maps an entry address to a microcode engine within the microsequencer, wherein a bit within the decoder is set to enable the selection signal.