Analog switch including two complementary MOS field-effect transitors

Abstract

An analog switch includes two complementary MOS field-effect transitors ( 10, 12 ) whose source-drain circuits are located in parallel between the input terminal ( 18 ) and the output terminal ( 20 ) of the switch. A control signal for controlling the switch is applied to the gate of the MOS field-effect transistor ( 12 ) of the one channel type directly and to the gate of the MOS field-effect transistor ( 10 ) of the other channel type via a negator ( 16 ). Between the input terminal ( 18 ) and output terminal ( 20 ) of the switch the series source-drain circuits of three MOS field-effect transistors ( 22, 24, 26 ) are inserted, whereby the MOS field-effect transistor ( 24 ) located in the middle of the series circuit has a channel type opposite that of the other two MOS field-effect transistors ( 22, 26 ). The gates of all MOS field-effect transistors of the other channel type are each interconnected. The threshold voltages of the three MOS field-effect transistors ( 22, 24, 26 ) of the series circuit are lower than the threshold voltages of the two complementary MOS field-effect transitors ( 10, 12 ) whose source-drain circuits are connected in parallel.

What is claimed is:  
     
       1. An analog switch comprising two complementary MOS field-effect transistors having source-drain circuits located in parallel between an input terminal and an output terminal of the switch, a control signal for controlling the switch being applied to the gate of the MOS field-effect transistor of the one channel type directly and to the gate of the MOS field-effect transistor of the other channel type via an inverter, a series of source-drain circuits of three MOS field-effect transistors ( 22 ,  24 ,  26 ) are inserted between the input terminal ( 18 ) and the output terminal ( 20 ) of the switch, whereby the MOS field-effect transistor ( 24 ) located in the middle of the series circuit has a channel type opposite that of the other two MOS field-effect transistors ( 22 ,  26 ), wherein the gates of all MOS field-effect transistors of the other channel type are each interconnected and that the threshold voltages of the three MOS field-effect transistors ( 22 ,  24 ,  26 ) of the series circuit are lower than the threshold voltages of the two complementary MOS field-effect transistors ( 10 ,  12 ) whose source-drain circuits are connected in parallel.