Method and apparatus to produce a random bit sequence

Abstract

A circuit includes a first oscillator having transistors to produce a first signal with random variations resulting from device channel resistance of the transistors.

What is claimed is:  
     
       1. A circuit comprising: 
       a first oscillator having transistors to produce a first signal with random variations resulting from device channel resistance of the transistors; and  
       a second oscillator to produce a second signal, the first signal applied to sample the second signal.  
     
     
       2. The circuit of  claim 1  further comprising: 
       a sampling circuit to which the first signal is applied to sample the second signal.  
     
     
       3. The circuit of  claim 1 , the first oscillator further comprising: a logic gate coupled to a node of the oscillator to which the transistors are also coupled, the logic gate having a gate area adapted to reduce the capacitance at the node. 
     
     
       4. A circuit comprising: 
       a first oscillator to produce a first signal; and  
       a second oscillator having transistors to produce a second signal with random variations resulting from device channel resistance of the transistors, the second signal applied to sample the first signal.  
     
     
       5. The circuit of  claim 4  further comprising: 
       a sampling circuit to which the second signal is applied to sample the first signal.  
     
     
       6. The circuit of  claim 4  in which the second oscillator further comprises: 
       a logic gate coupled to a node of the second oscillator to which the transistors are also coupled, the logic gate having a gate area adapted to reduce the capacitance at the node.  
     
     
       7. The circuit of  claim 4 , the second oscillator further comprising: 
       a plurality of stages, each stage having transistors with device channel resistance which contributes to the random variations of the second signal.  
     
     
       8. A method comprising: 
       applying device channel resistance of transistors to produce random variations in a first signal; and  
       applying the first signal to sample a second signal.  
     
     
       9. The method of  claim 8  further comprising: 
       providing a logic gate coupled to the transistors, the logic gate having a gate area adapted to reduce a capacitance to which the first signal is subjected.  
     
     
       10. A system comprising: 
       a processor coupled to a memory by way of a bus, the processor comprising a first oscillator having transistors to produce a first signal with random variations resulting from device channel resistance of the transistors; and  
       a second oscillator to produce a second signal, the first signal applied to sample the second signal.  
     
     
       11. The system of  claim 10 , the processor further comprising: 
       a logic gate coupled to a node of the first oscillator to which the transistors are also coupled, the logic gate having a gate area adapted to reduce the capacitance at the node.  
     
     
       12. A system comprising: 
       a processor coupled to a memory by way of a bus, the processor comprising  
       a first oscillator to produce a first signal; and  
       a second oscillator having transistors to produce a second signal with random variations resulting from device channel resistance of the transistors, the second signal applied to sample the first signal.  
     
     
       13. The system of  claim 12  the processor further comprising: 
       a sampling circuit to which the second signal is applied to sample the first signal.  
     
     
       14. The system of  claim 12  in which the processor further comprises: 
       a logic gate coupled to a node of the second oscillator to which the transistors are also coupled, the logic gate having a gate area adapted to reduce the capacitance at the node.