Circuit board, a method for manufacturing same, and a method of electroless plating

Abstract

A circuit board is provided, wherein electroless plating to fill via-holes can be controlled uniformly with desirable reproducibility, and via-hole portions can be identified from the surface of the substrate after forming a second conductor thereon. The specific circuit board is obtained by applying a potential higher then the potential of the electroless plating to the conductor on the surface when filling the via-holes by electroless plating. In the circuit board, via-hole portions can be identified optically, because the via-hole portion differs from the second conductor in surface condition, such as when a dent is formed.

What is claimed is:  
     
       1. A method of manufacturing a circuit board including a first conductor, a second conductor, an insulating layer formed between said first conductor and said second conductor, the second conductor being spaced from the first conductor by the insulating layer so as to be electrically insulated from the first conductor, and a third conductor formed in said insulating layer in order to electrically connect said first conductor and said second conductor, comprising the steps of: 
       performing electroless plating by an electroless plating reaction, to form the third conductor to connect the first conductor and the second conductor; and  
       while performing electroless plating, applying a potential, higher than a potential of the electroless plating reaction during the electroless plating, to said second conductor from an external power source.  
     
     
       2. The method of manufacturing a circuit board according to  claim 1 , further comprising the steps of: 
       forming said first conductor onto an insulating substrate;  
       forming said insulating layer onto said first conductor and said insulating substrate;  
       forming material for said second conductor on said insulating layer;  
       performing a patterning of said material for said second conductor, to form said second conductor; and  
       forming via-holes through the insulating layer, wherein said forming via-holes includes performing a laser or plasma processing using said second conductor as a mask.  
     
     
       3. The method of manufacturing a circuit board according to  claim 1 , further comprising the steps of: 
       forming said first conductor onto an insulating substrate;  
       laminating an insulating film having material for said second conductor on its surface onto said first conductor and said insulating substrate;  
       performing a patterning of said material for said second conductor, to form said second conductor; and  
       forming via-holes through the insulating layer, wherein said forming via-holes includes a step of performing a laser or plasma processing using said second conductor as a mask.  
     
     
       4. The method of manufacturing a circuit board according to  claim 1 , including the further step of forming via-holes through said insulating layer; and wherein, during the electroless plating, the circuit board is immersed in an electroless plating solution. 
     
     
       5. The method of manufacturing a circuit board according to  claim 1 , including the further step of forming via-holes, exposing the first conductor, in the insulating layer, and wherein the electroless plating is performed to form the third conductor in the via-holes. 
     
     
       6. The method of manufacturing a circuit board according to  claim 1 , wherein the potential higher than the potential of the electroless plating reaction is applied to the second conductor such that when the third conductor contacts the second conductor during the electroless plating, electroless plating of the third conductor at the second conductor stops. 
     
     
       7. The method of manufacturing a circuit board according to  claim 1 , wherein said potential applied to the second conductor is in a range of +0.1 to +1.5 V in comparison with the potential of the electroless plating reaction. 
     
     
       8. The method of manufacturing a circuit board according to  claim 1 , wherein said potential applied to the second conductor is in a range of +0.4 to +0.7 V in comparison with the potential of the electroless plating reaction. 
     
     
       9. The method of manufacturing a circuit board according to  claim 1 , wherein said third conductor is made of a material selected from the group consisting of copper, nickel, silver, gold, palladium, solder and cobalt. 
     
     
       10. The method of manufacturing a circuit board according to  claim 1 , further comprising a step of covering exposed surfaces of said second conductor and said third conductor with a fourth conductor. 
     
     
       11. The method of manufacturing a circuit board according to  claim 1 , wherein in said performing electroless plating, the electroless plating originates from the first conductor, electrically insulated from the second conductor. 
     
     
       12. A method of electroless plating for depositing an electrolessly plated conductor on a surface of a first conductor, comprising the steps of: 
       providing said first conductor and a second conductor, which is electrically insulated from said first conductor, overlying a surface of a body which is going to be plated;  
       performing electroless plating to deposit said electrolessly plated conductor, by an electroless plating reaction; and  
       applying a potential higher than-the potential of said electroless plating reaction to said second conductor during said electroless plating, said potential being applied from an external power source.  
     
     
       13. The method of electroless plating according to  claim 12 , wherein said second conductor is provided at a position separated from the surface of the body, in electroless plating solution used for the electroless plating. 
     
     
       14. The method of electroless plating according to  claim 12 , wherein said potential to be applied to said second conductor is in a range of +0.1 to +1.5 V in comparison with the potential of the electroless plating reaction. 
     
     
       15. The method of electroless plating according to  claim 12 , wherein said potential to be applied to said second conductor is in a range of +0.4 to +0.7 V in comparison with the potential of the electroless plating reaction. 
     
     
       16. The method of electroless plating according to  claim 12 , wherein said second conductor and said first conductor are separated by an insulating layer. 
     
     
       17. The method of electroless plating according to  claim 12 , wherein the first conductor and the second conductor are separated by an insulating layer, said insulating layer has a groove therethrough exposing the first conductor, and wherein the electrolessly plated conductor is deposited in the groove. 
     
     
       18. Thee method of electroless plating according to  claim 12 , wherein the first conductor and the second conductor are separated by an insulating layer, said insulating layer has a hole exposing the first conductor, and wherein the electrolessly plated conductor is deposited in the hole. 
     
     
       19. The method of electroless plating according to  claim 12 , wherein the potential higher than the potential of the electroless plating reaction is applied to the second conductor such that when the electrolessly plated conductor contacts the second conductor during the electroless plating, electroless plating of the electrolessly plated conductor at the second conductor stops. 
     
     
       20. The method of electroless plating according to  claim 12 , wherein the first conductor is insulated from the second, conductor by an insulating layer, the insulating layer having a surface furthest from the first conductor, and wherein the second conductor is positioned between the first conductor and said surface of the insulating layer. 
     
     
       21. The method of electroless plating according to  claim 12 , wherein the first conductor is insulated from the second conductor by an insulating layer, the insulating layer having at least two holes extending into the insulating layer from a surface thereof, two of the holes extending into the insulating layer to different depths and each exposing a portion of the first conductor which respectively is at a different depth from the surface. 
     
     
       22. The method of electroless plating according to  claim 12 , wherein in said performing electroless plating, the electrolessly plated conductor is deposited originating from the first conductor, electrically insulated from the second conductor.