Offset compensation in parallel analogue-digital converters

Abstract

The present invention relates to a method of offset compensating a parallel analogue-digital converter that includes at least two channels (35), where the analogue to digital conversion takes place simultaneously in the various channels but offset relative to respective channels. An analogue input signal (10) to the analogue-digital converter is multiplied by +1 or by -1 in accordance with an arbitrary pattern and the output signal from the analogue-digital converter is multiplied by +1 or by -1 in accordance with the same arbitrary pattern as that by which the input signal was multiplied. The invention also includes a parallel analogue-digital converter for carrying out the method.

What is claimed is:  
     
       1. A method of offset compensating a parallel analogue-digital converter that includes at least two channels, where an analogue-digital conversion in said channels takes place in a time offset relative to one another, comprising: 
       multiplying the analogue input signal to the analogue-digital converter by +1 or −1 in accordance with an arbitrary pattern;  
       multiplying the output signal from the analogue-digital converter by +1 or −1 in accordance with the same arbitrary pattern as that used to multiply the input signal;  
       subtracting a mean value of the output signal from each channel prior to multiplying said output signal by said arbitrary pattern; and  
       subjecting the output signal to an interference suppression process prior to multiplying said output signal by said arbitrary pattern.  
     
     
       2. A method according to  claim 1 , wherein said process is a LMS process (Least Mean Square). 
     
     
       3. A method according to  claim 1 , comprising creating said arbitrary pattern by controlling a sign changing means by means of a PRBS-generator (Pseudo Random Binary Sequence). 
     
     
       4. A parallel channel analogue-digital converter which includes at least two channels and with which analogue-digital conversion in the various channels takes place in a time offset relative to each channel, wherein the parallel channel analogue-digital converter includes: 
       means for multiplying the analogue input signal to the analogue-digital converter by +1 or by −1 in accordance with arbitrary pattern;  
       means for multiplying the output signal from the analogue-digital converter by +1 or by −1 in accordance with the same arbitrary pattern as that by which the input signal was multiplied;  
       means for calculating the mean value of the output signal from each channel in the parallel channel analogue-digital converter;  
       means for subtracting said mean value from said output signal; and  
       means for subjecting the output signal to an interference suppression process prior to multiplying the output signal by said arbitrary pattern.  
     
     
       5. A parallel channel analogue-digital converter according to  claim 4 , wherein the means for multiplying the analogue input signal to the analogue-digital converter by +1 or by −1 in accordance with an arbitrary pattern is common to all channels. 
     
     
       6. A parallel channel analogue-digital converter according to  claim 4 , wherein said means for multiplying the analogue input signal to the analogue-digital converter by +1 or −1 according to an arbitrary pattern is individual to each channel. 
     
     
       7. A parallel channel analogue-digital converter according to  claim 4 , wherein the means for multiplying the input signal to the analogue-digital converter and the output signal from said analogue-digital converter by +1 or −1 in accordance with an arbitrary pattern is a sign changing means controlled by PRBS-generator (Pseudo Random Binary Sequence). 
     
     
       8. A parallel channel analogue-digital converter according to  claim 4 , wherein the analogue-digital conversion is of the successive approximation type. 
     
     
       9. A parallel channel analogue-digital converter according to  claim 4 , wherein said process is an LMS process (Least Mean Square).