Corrosion resistant imager

Abstract

A radiation imager is disclosed that is resistant to degradation due to moisture by either contact pad corrosion, guard ring corrosion or by photodiode leakage. A contact pad of a large area imager is disclosed that is formed into three distinct and electrically connected regions. The resulting structure of the contact pad regions forms reliable contact that is resistant to corrosion damage. Also disclosed is a data line of an imager, or a display, the resistance of which is reduced by patterning an aluminum (Al) line on top of a transistor island structure, with the formed data line preferably being encapsulated. In addition, a guard ring having first and second regions and photosensitive element are disclosed. The second region comprises an electrical contact between ITO and underlying metal and a second tier which acts as a moisture barrier and is preferably disposed at the corner of the guard ring and separated from the contact pads of the imager in such a manner as to minimize corrosion. The photosensitive element has a multitier passivation layer disposed between the top contact layer and an amorphous silicon photosensor island except for a selected contact area on the top surface of the photosensor island, where the top contact layer is in electrical contact with the amorphous silicon material of the photosensor island. The passivation layer includes a first tier inorganic barrier layer which is disposed at least over the sidewalls of the photosensor island.

What is claimed is:  
     
       1. A contact pad for a pixel array, said contact pad comprising respective first, second and third regions, each of said regions having a continuous gate contact layer which is overlayed by a continuous source-drain contact layer, said first and second regions further comprising a continuous upper conductor layer comprising indium tin oxide (ITO), said continuous upper conductor layer being disposed over said source-drain contact layer; 
       said contact pad third region comprising a first via providing electrical coupling between said gate contact layer and said source-drain contact layer, said contact pad third region further being disposed to provide electrical contact to said pixel array;  
       said contact pad second region comprising a second via providing electrical coupling between said source-drain contact layer and said upper conductive layer;  
       said contact pad first region being adapted to provide electrical coupling between said upper conductive layer and an external device to said pixel array, said upper conductive layer being separated from said gate contact layer and said source-drain contact layer by intermediate passivation layers in said first contact pad region.  
     
     
       2. The contact pad according to  claim 1 , wherein said continuous upper conductor layer comprises indium tin oxide material (ITO) and has an upper surface and a lower surface and wherein said upper surface of said ITO material in said first region is exposed and said lower surface of said ITO material is separated from said continuous gate contact by at least one dielectric layer, said ITO material in said second region being disposed in electrical contact with said continuous source-drain contact layer. 
     
     
       3. The contact pad according to  claim 2 , wherein said ITO material in said second region is covered at least in part by a barrier layer and, said source-drain layer in said third region is covered at least in part by at least one dielectric layer and said barrier layer. 
     
     
       4. The contact pad according to  claim 2 , wherein said first region further comprises a first layer of dielectric disposed over said gate contact layer, a layer of thin film transistor (TFT) passivation layer overlaying said first dielectric layer and a diode passivation layer overlaying said TFT passivation layer with both said TFT and diode passivation layers separating said first dielectric layer from said ITO material. 
     
     
       5. The contact pad according to  claim 2 , wherein said second region further comprises a first layer of dielectric disposed over said gate contact layer and said contact pad in said second region further comprises an arrangement separating said source-drain contact layer and said ITO material, said arrangement including: 
       (a) a layer of a thin film transistor (TFT) passivation layer disposed over edge portions of said source-drain contact material in said second region so as to leave the central region of said source-drain contact layer at said second region free of said layer of TFT passivation layer;  
       (b) a diode passivation layer disposed over said TFT passivation layer in said second region so as to leave said central region of said source-drain contact at said second region free of said TFT and diode passivation layers; and  
       (c) a layer of polymer having sloped sidewalls covering said TFT and diode passivation layers in said second region and a portion of said central region of said source-drain contact layer at said second region but disposed so as to leave some of said central region of said source-drain contact layer at said second region free of said layer of polymers and said TFT and diode layers.  
     
     
       6. The contact pad according to  claim 5 , wherein said diode passivation layer comprises silicon nitride and has a thickness in the range between about 0.5 microns and about 1.5 microns. 
     
     
       7. The contact pad according to  claim 1 , wherein said third region is electrically coupled to an address line in said pixel array. 
     
     
       8. The contact pad according to  claim 1 , wherein said upper conductor layer of indium tin oxide has a thickness in the range between about 50 nanometers and about 200 nanometers.