Stable reference voltage generator circuit

Abstract

A circuit for generating a stable reference voltage (Vref) as temperature and process parameters vary, including at least one field-effect transistor (M 1 ) and an associated resistive bias element (R) connected in series between a supply voltage (Vcc) and ground (GND), further includes a second field-effect transistor (M 2 ) connected to the first transistor such that the reference voltage (Vref) can be picked up as the difference between the respective threshold voltages of the two transistors. This provides a reference voltage which is uniquely stable against variations in temperature and process parameters.

What is claimed is:  
     
       1. A circuit comprising: 
       a first diode-connected natural field effect transistor connected, in series with a load element, between first and second power supply connections; said first transistor and said load element having an intermediate node therebetween;  
       a second diode-connected natural field effect transistor connected between said intermediate node and an output node;  
       wherein said first and second transistors are of opposite conductivity types, and said first transistor has a threshold voltage whose absolute value is more than the absolute value of the threshold voltage of said second transistor;  
       whereby said output terminal provides a voltage which is equal to the threshold voltage of said first transistor reduced by the absolute value of the threshold voltage of said second transistor.  
     
     
       2. The circuit of  claim 1 , wherein said first transistor has a threshold voltage whose absolute value is more than twice the absolute value of the threshold voltage of said second transistor. 
     
     
       3. The circuit of  claim 1 , wherein said first field effect transistor is a P-channel field effect transistor, and said first power supply is a positive power supply. 
     
     
       4. The circuit of  claim 1 , wherein said load is a transistor having a gate connected to a constant voltage. 
     
     
       5. The circuit of  claim 1 , further comprising an additional load element operatively connected at said output node to continually draw current through said second transistor. 
     
     
       6. An integrated circuit comprising: 
       a diode-connected natural P-channel field effect transistor connected between a chip ground and an intermediate node;  
       a load connected between said intermediate node and a positive power supply connection; and  
       a diode-connected natural N-channel field effect transistor connected between said intermediate node and an output node;  
       wherein said P-channel transistor has a threshold voltage whose absolute value is more than the absolute value of the threshold voltage of said N-channel transistor;  
       whereby said output node provides a reference voltage above chip ground which is equal to the threshold voltage of said P-channel transistor reduced by the absolute value of the threshold voltage of said N-channel transistor.  
     
     
       7. The integrated circuit of  claim 6 , further comprising an additional load element operatively connected at said output node to continually draw current through said N-channel transistor. 
     
     
       8. The integrated circuit of  claim 6 , wherein said P-channel field effect transistor has a threshold value whose absolute value is more than twice the absolute value of the threshold voltage of said N-channel field effect transistor. 
     
     
       9. The integrated circuit of  claim 6 , wherein said load is a resistor. 
     
     
       10. A CMOS integrated circuit, comprising: 
       logic circuitry including both P-channel and N-channel field effect transistors; said N-channel logic transistors each including a vertical doping profile, in respective channel regions thereof, which includes a surface doping concentration corresponding to a VT-adjust implant; and said P-channel logic transistors each including a vertical doping profile, in respective channel regions thereof, which includes a surface doping concentration corresponding to a VT-adjust implant; and  
       a reference voltage circuit which includes  
       a diode-connected P-channel field effect transistor connected between a chip ground and an intermediate node;  
       a load connected between said intermediate node and a positive power supply connection; and  
       a diode-connected N-channel field effect transistor connected between said intermediate node and an output node;  
       whereby said output node provides a reference voltage above chip ground which is equal to the threshold voltage of said PMOS transistor reduced by the absolute value of the threshold voltage of said N-channel transistor;  
       wherein said P-channel and N-channel transistors of said reference voltage circuit do not include any dopant concentration in the respective channels thereof corresponding to said VT-adjust implant.  
     
     
       11. The integrated circuit of  claim 10 , wherein said load is a resistor. 
     
     
       12. The integrated circuit of  claim 10 , further comprising an additional load element operatively connected at said output node to continually draw current through said N-channel transistor. 
     
     
       13. The integrated circuit of  claim 10 , further comprising a differential amplifier connected at said output node to receive the voltage from said output connection and to receive a second voltage, and to provide a differential feedback signal which is dependent on the difference between said the voltage from said output connection and said second voltage. 
     
     
       14. A circuit for generating a stable reference voltage as temperature and process parameters vary, comprising: 
       at least one natural field-effect transistor and an associated resistive bias element connected in series between a supply voltage and ground, and  
       a second natural field-effect transistor interposed between the first transistor and an output node, and not directly connected to said supply voltage nor to ground, such that said reference voltage can be picked up as the difference between the respective threshold voltages of the transistors.  
     
     
       15. A circuit according to  claim 14 , wherein the second of said transistors is a natural n-channel MOS. 
     
     
       16. A circuit according to  claim 14 , wherein both said transistors are connected in the circuit in a diode configuration with their respective gate and drain terminals connected together. 
     
     
       17. A circuit according to  claim 14 , wherein the second transistor has at least one terminal in common with the first transistor. 
     
     
       18. A circuit according to  claim 17 , wherein said common terminals are the source of the first transistor and the drain of the second transistor, respectively. 
     
     
       19. A circuit according to  claim 17 , wherein the second transistor has its drain terminal connected to the resistive element and its source terminal available for picking up the reference voltage.