US6399460B1ExpiredUtility

Semiconductor device

76
Assignee: MITSUBISHI ELECTRIC CORPPriority: Jul 12, 1999Filed: Oct 5, 2000Granted: Jun 4, 2002
Est. expiryJul 12, 2019(expired)· nominal 20-yr term from priority
H10W 10/17H10W 10/014H10W 10/181H10W 10/061H10P 90/1906H10D 30/6706H10D 30/6711H10D 30/6713H10D 30/60Y10S257/913
76
PatentIndex Score
20
Cited by
2
References
1
Claims

Abstract

A method of manufacturing a semiconductor device including the steps of (a) forming an element isolation insulating film in an element isolation region of a SOI substrate of a stacked structure in which a semiconductor substrate, insulating layer, and semiconductor layer are stacked in this order, and (b) forming, in an element formation region of the SOI substrate, a transistor having a channel formation region selectively disposed in a main surface of the semiconductor layer, a gate structure on the channel formation region, and source/drain regions disposed is the main surface of the semiconductor layer and the adjacent channel formation region. The method also includes the step of (c) selectively growing, after said steps (a) and (b), a polycrystal semiconductor layer on the source/drain regions in a self-aligned manner, which is prescribed by the element isolation insulating film and the gate structure.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
       1. A method of manufacturing a semiconductor device comprising the steps of: 
       (a) forming an element isolation insulating film in an element isolation region of a SOI substrate of a stacked structure in which a semiconductor substrate, insulating layer, and semiconductor layer are stacked in this order;  
       (b) forming, in an element formation region of said SOI substrate, a transistor having a channel formation region selectively disposed in a main surface of said semiconductor layer, a gate structure on said channel formation region, and source/drain regions disposed in said main surface of said semiconductor layer and adjacent said channel formation region; and  
       (c) selectively growing, after said steps (a) and (b), a polycrystal semiconductor layer on said source/drain regions in a self-aligned manner, by means of said element isolation insulating film and said gate structure.

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