Semiconductor memory device and restoration method therefor

Abstract

A semiconductor memory device includes: a plurality of memory cell regions, each comprising at least one memory cell; a non-volatile memory section which accepts external writing; and unselecting means for designating at least one of the plurality of memory cell regions to be inaccessible based on data written to the non-volatile memory section. At least one operation type is performed for at least one accessible memory cell region, which is not designated to be inaccessible, among the plurality of memory cell regions.

What is claimed is:  
     
       1. A semiconductor memory device comprising: 
       a plurality of memory cell regions, each comprising at least one memory cell;  
       a non-volatile memory section which accepts external writing; and  
       unselecting means for designating at least one of the plurality of memory cell regions to be inaccessible based on data written to the non-volatile memory section,  
       wherein at least one operation type is performed for at least one accessible memory cell region, which is not designated to be inaccessible, among the plurality of memory cell regions.  
     
     
       2. A semiconductor memory device according to  claim 1 , further comprising address conversion means for assigning a consecutive sequence of external addresses to the at least one accessible memory cell region. 
     
     
       3. A semiconductor memory device according to  claim 2 , wherein, if an internal address which is generated by adding a predetermined value to an external address coincides with an existing internal address when assigning the consecutive sequence of external addresses to the at least one accessible memory cell region, one of the plurality of memory cell regions corresponding to the generated internal address is designated to be inaccessible. 
     
     
       4. A semiconductor memory device according to  claim 1 , wherein, based on the data written to the non-volatile memory section, the unselecting means designates at least one of the plurality of memory cell regions to be inaccessible to one operation type among the at least one operation type, and yet accessible to the other operation types among the at least one operation type. 
     
     
       5. A semiconductor memory device according to  claim 1 , 
       wherein the semiconductor memory device comprises a plurality of memory cell blocks capable of accepting a block erase operation, and  
       wherein, when designating at least one of the plurality of memory cell regions to be inaccessible based on the data written to the non-volatile memory section, the unselecting means designates at least one of the plurality of memory cell blocks to be inaccessible.  
     
     
       6. A semiconductor memory device according to  claim 5 , 
       wherein the plurality of memory cell blocks includes at least one memory cell block having a different capacity.  
     
     
       7. A semiconductor memory device according to  claim 5 , 
       wherein the semiconductor memory device comprises a plurality of banks, each comprising the plurality of memory cell blocks, such that the plurality of memory cell blocks are capable of dual work operation, and  
       wherein, when designating at least one of the plurality of memory cell regions to be inaccessible based on the data written to the non-volatile memory section, the unselecting means designates at least one of the plurality of banks to be inaccessible.  
     
     
       8. A semiconductor memory device according to  claim 7 , wherein at least one of the plurality of banks includes at least one memory cell block having a different capacity. 
     
     
       9. A semiconductor memory device according to  claim 6 , wherein the address conversion means is capable of changing an address position of the at least one memory cell block having the different capacity. 
     
     
       10. A semiconductor memory device according to  claim 1 , wherein the non-volatile memory section is provided in a portion of a non-volatile memory cell which is capable of programming at once. 
     
     
       11. A method for restoring the semiconductor memory device according to  claim 1  when the semiconductor memory device includes a defective memory cell, comprising the steps of: 
       storing an address of the defective memory cell in the non-volatile memory section; and  
       designating, by means of the unselecting means, one of the plurality of memory cell regions that includes the defective memory cell to be inaccessible, based on the data written to the non-volatile memory section.  
     
     
       12. A method according to  claim 11 , further comprising the step of: 
       designating, by means of the unselecting means, one of the plurality of memory cell regions that includes the defective memory cell to be inaccessible only to an operation type which causes an error, based on the data written to the non-volatile memory section.