Method and apparatus for a bias generator with output current dependent on clock frequency

Abstract

An electronic circuit generates a bias current that is proportional to a frequency of a reference clock signal in a switched capacitor circuit. The electronic circuit includes a capacitive circuit selectively coupled to a transistor supplied by a voltage reference circuit. During a first phase the capacitive circuit is charged by a current from the transistor, and during the second phase the capacitive circuit is discharged to ground. The duration of each phase is related to the reference clock signal. The average current corresponds to a bias signal and is filtered to reduce ripple in the bias signal before the bias signal is received by the switched capacitor circuit. The capacitive circuit is configured with a first and second capacitor arranged in a complimentary out-of-phase configuration. During a first phase, the first capacitor is charged and the second capacitor is discharged. During the second phase, the second capacitor is charged and the first capacitor is discharged. The out-of-phase configuration reduces the size of each capacitor used for the capacitive circuit as compared to a single capacitor. The configuration also reduces ripple in the current, which reduces the size of the filter. The frequency dependant current is mirrored into the switched-capacitor circuit. In one example, the electronic circuit is implemented as an integrated circuit including “on-chip” capacitors that have inherent parasitic capacitances associated therewith. In this instance, the type and orientation of the electronic circuit capacitors should match the switched capacitor circuit capacitors such that parasitic effects track one another.

We claim:  
     
       1. An apparatus that produces a frequency dependent bias signal for a switched capacitor circuit, wherein the frequency dependent bias signal is dependent on a reference clock signal that has a corresponding clock frequency, and the switched capacitor circuit includes a type of capacitive circuit, the apparatus comprising: 
       a control circuit that is arranged to produce a control signal in response to a reference potential;  
       a controlled circuit that is arranged to produce a regulated potential in response to the control signal, wherein the regulated potential is related to the reference potential;  
       a capacitive circuit that is the same type as the type of capacitive circuit within the switched capacitor circuit;  
       a discharging circuit that is arranged to discharge the capacitive circuit in response to a clock signal when the clock signal corresponds to a first logic level;  
       a charging circuit that is arranged to couple a charging current to the capacitive circuit in response to the control signal when the clock signal corresponds to a second logic level that is different from the first logic level such that the charging current charges the capacitive circuit; and  
       a sense circuit that is arranged to produce the frequency dependent bias signal in response to an average of the charging current, wherein the average of the charging current is related to the clock signal.  
     
     
       2. The apparatus of  claim 1 , wherein the capacitive circuit charges to the regulated potential while the clock signal corresponds to the second logic level. 
     
     
       3. The apparatus of  claim 1 , wherein the regulated potential equals the reference potential. 
     
     
       4. The apparatus of  claim 1 , the controlled circuit further comprising a MOS transistor that is arranged to couple the charging current to the capacitive circuit. 
     
     
       5. The apparatus of  claim 1 , wherein the switched capacitor circuit has an associated power consumption that decreases when the corresponding clock frequency of the reference clock signal decreases. 
     
     
       6. The apparatus of  claim 1 , wherein the capacitive circuit is arranged to match an orientation of the type of capacitive circuit within the switched capacitor circuit such that effects from parasitic capacitances affect the apparatus and the switched capacitor circuit similarly. 
     
     
       7. The apparatus of  claim 1 , wherein the corresponding clock frequency and the frequency dependent bias signal are linearly related to one another when a time associated with charging the capacitive circuit is within an associated pulse-width of the clock signal. 
     
     
       8. The apparatus of  claim 1 , wherein the corresponding clock frequency and the frequency dependent bias signal are non-linearly related to one another when a time associated with charging the capacitive circuit is greater than the associated pulse-width of the clock signal. 
     
     
       9. The apparatus of  claim 1 , further comprising a ripple filter that is arranged to reduce a ripple associated with the frequency dependent bias signal. 
     
     
       10. The apparatus of  claim 1 , wherein the clock signal is related to the reference clock signal by a scaling factor. 
     
     
       11. The apparatus of  claim 1 , wherein the clock signal is a non-overlapping type of clock signal that is related to the reference clock signal. 
     
     
       12. The apparatus of  claim 1 , further comprising a second capacitive circuit that is arranged to charge as the capacitive circuit discharges and arranged to discharge as the capacitive circuit charges such that the frequency dependent bias signal is produced by a complimentary out-of-phase operation of the capacitive circuit in combination with the second capacitive circuit, whereby the size of each capacitive circuit may be reduced in size. 
     
     
       13. An apparatus that generates a bias signal that is dependent on a reference clock signal having a corresponding clock frequency and a corresponding pulse-width, the apparatus comprising: 
       a controlled current circuit that is arranged to produce a charging current when a sensed potential at a sense node is different from a reference potential;  
       a first capacitive circuit;  
       a first charging circuit that is arranged to couple the sense node to the first capacitive circuit in response to a first phase of a first clock signal such that the charging current charges the first capacitive circuit to a first charged potential during a first charging phase;  
       a first discharging circuit that is arranged to discharge the first capacitive circuit in response to a second phase of the first clock signal;  
       a second capacitive circuit;  
       a second charging circuit that is arranged to couple the sense node to the second capacitive circuit in response to a first phase of a second clock signal such that the charging current charges the second capacitive circuit to a second charged potential during a second charging phase;  
       a second discharging circuit that is arranged to discharge the second capacitive circuit in response to the a second phase of the second clock signal; and  
       an averaging circuit that is arranged to produce the bias signal in response to an average charging current, wherein the average charging current corresponds to an average of the charging current that is produced by the controlled current circuit such that the bias signal changes with changes in the reference clock signal.  
     
     
       14. The apparatus of  claim 13 , wherein the first phase of the first clock signal and the first phase of the second clock signal have equal pulse-widths that are related to the corresponding pulse-width of the reference clock signal. 
     
     
       15. The apparatus of  claim 13 , wherein the first phase of the first clock signal and the second phase of the second clock signal are aligned in time. 
     
     
       16. The apparatus of  claim 13 , wherein the first and second clock signals are derived from the reference clock signal, and the first phase of the first clock signal and the first phase of the second clock signal are non-overlapping with respect to one another. 
     
     
       17. The apparatus of  claim 13 , further comprising a ripple filter that is arranged to minimize a ripple associated with the bias signal. 
     
     
       18. The apparatus of  claim 13 , the controlled current circuit further comprising a transistor that is biased to provide the charging current to the sense node when the sensed potential at the sense node is different from the reference potential. 
     
     
       19. The apparatus of  claim 13 , wherein a power consumption associated with a subsequent circuit that is biased by the bias signal decreases as the corresponding clock frequency decreases. 
     
     
       20. The apparatus of  claim 19 , wherein the subsequent circuit includes another capacitive circuit that is matched in type and orientation to the first and second capacitive circuits such that effects from parasitic capacitances effect the apparatus and the subsequent circuit similarly. 
     
     
       21. The apparatus of  claim 13 , wherein the corresponding clock frequency and the bias signal have a linear relationship with respect to one another when the first and the second charged potentials are substantially the same as the reference potential at the end of the first and second charging phases respectively. 
     
     
       22. The apparatus of  claim 13 , wherein the corresponding clock frequency and the bias signal have a non-linear relationship with respect to one another when the first and the second charged potentials are substantially different from the reference potential at the end of the first and second charging phases respectively. 
     
     
       23. A method for generating a frequency dependent bias signal, comprising: 
       sensing a potential at a sense node to produce a sensed potential;  
       coupling a charging current to the sense node when the sensed potential is different from a reference potential;  
       coupling the sense node to a first capacitive circuit such that the first capacitive circuit charges with a first charging current during a first phase of a first clock signal;  
       decoupling the sense node from the first capacitive circuit during a second phase of the first clock signal;  
       discharging the first capacitive circuit during the second phase of the first clock signal;  
       coupling the sense node to a second capacitive circuit such that the second capacitive circuit charges with a second charging current during a first phase of a second clock signal, wherein the first phase of the first clock signal is inactive when the first phase of the second clock signal is active;  
       decoupling the sense node from the second capacitive circuit during a second phase of the second clock signal;  
       discharging the second capacitive circuit during the second phase of the second clock signal; and  
       generating a bias signal in response to an average current that corresponds to an average of the first and second charging currents such that the bias signal is related to a frequency associated with the first and second clock signals.  
     
     
       24. The method in  claim 23 , further comprising suppressing a ripple associated with the bias signal. 
     
     
       25. The method in  claim 23 , further comprising coupling the biasing signal to another circuit that has an associated power consumption that is controlled by the frequency associated with the first and second clock signals such that a decrease in the frequency results in decreased power consumption in the another circuit. 
     
     
       26. The method in  claim 23 , further comprising: 
       coupling the biasing signal to another circuit; and  
       matching a type and orientation of another capacitive circuit to the first and second capacitive circuits, wherein the another capacitive circuit is included in the another circuit such that a parasitic effect in the another capacitive circuit is matched to parasitic effects in the first and second capacitive circuits.  
     
     
       27. An apparatus for providing a bias signal for a switched-capacitor circuit that uses a reference clock signal with a corresponding reference clock frequency, the apparatus comprising: 
       a means for producing a first clock signal is arranged to produce a first clock signal in response to the reference clock signal, the first clock signal having a first and second phase;  
       a means for producing a second clock signal is arranged to produce a second clock signal in response to the reference clock signal, the second clock signal having a first and second phase, wherein the first phase of the second clock signal is non-overlapping with respect to the first phase of the first clock signal;  
       a means for sensing is arranged to sense a sensed potential at a sense node;  
       a means for producing a current is arranged to provide a charging current when the sensed potential is different from a reference potential;  
       a first means for charging is arranged to couple the sense node to a first capacitive circuit such that the first capacitive circuit is charged with a first charging current to a first charged potential in response to the first phase of the first clock signal;  
       a first means for discharging is arranged to discharge the first capacitive circuit in response to the second phase of the first clock signal;  
       a second means for charging is arranged to couple the sense node to a second capacitive circuit such that the second capacitive circuit is charged with a second charging current to a second charged potential in response to the first phase of the second clock signal;  
       a second means for discharging is arranged to discharge the second capacitive circuit in response to the second phase of the second clock signal; and  
       an averaging means is arranged to produce the bias signal in response to an average of the charging current, wherein the average of the charging current corresponds to the first and second charging currents such that the average of the charging current is related to the reference clock frequency.  
     
     
       28. The apparatus of  claim 27 , wherein the power consumption of the switched-capacitor circuit decreases as the reference clock frequency decreases. 
     
     
       29. The apparatus of  claim 27 , further comprising a means for reducing ripple is arranged to reduce a ripple associated with the bias signal. 
     
     
       30. The apparatus of  claim 27 , wherein the first and second capacitive circuits are of a type and orientation that are matched to other capacitive circuits within the switched capacitor circuit.