Analog filtering with symmetrical timing using a single comparator

Abstract

Provided is a symmetrical filter that uses a single comparator. In addition to a voltage divider, a current regulator, and a comparator, the filter of the invention provides control logic that turns on or off a pull up switch and/or pull down switch in order to fully charge or fully discharge a capacitor. Accordingly, in one aspect, the invention is a control logic for a symmetrical filter. Furthermore, timing logic is provided to provide for a more rigorous symmetrical filter performance.

We claim:  
     
       1. A symmetrical filter, comprising: 
       an input voltage node (Vin) for receiving an input signal;  
       an intermediate node;  
       a comparator coupled to a supply voltage node (Vsup), a ground voltage node (Vgnd), a capacitor voltage node (Vcap), and a reference voltage node (Vref);  
       a voltage divider coupled between Vsup and the Vgnd and also connected to the Vref;  
       a capacitor coupled between the Vgnd and the Vcap;  
       a current regulator coupled to the Vsup, the Vgnd, and the Vcap;  
       an invertor block coupled between the Vin and the intermediate node;  
       a pull-up switch coupled between the Vsup and the Vcap;  
       a pull down switch coupled between the Vgnd and the Vcap;  
       a control logic coupled to the pull up switch, the pull down switch and the Vin; and  
       an output node (Vout) coupled to the comparator for providing an output signal.  
     
     
       2. The symmetrical filter of  claim 1  wherein the current regulator comprises: 
       a first current source coupled between the Vsup and an input switch having an output connected to the Vcap and an input connected to the intermediate node; and  
       a second current source coupled between the Vgnd and the input switch.  
     
     
       3. The symmetrical filter of  claim 1  wherein the invertor block comprises: 
       a first inverter coupled between and the Vin and the intermediate node; and  
       a second inverter coupled between the intermediate node and the control logic.  
     
     
       4. The symmetrical filter of  claim 1  wherein the control logic comprises: 
       a NAND gate having a first input coupled to the inverter block, a second input coupled to Vout, and an output connected to the pull up switch; and  
       a NORgate having a first input coupled to the inverter block, a second input coupled to the Vout, and an output connected to the pull down switch.  
     
     
       5. The symmetrical filter of  claim 1  wherein the voltage divider comprises a first resistor coupled between Vsup and Vref, and a second resistor coupled between Vref and Vgnd. 
     
     
       6. The symmetrical filter of  claim 1  wherein the pull up switch comprises a PMOS device. 
     
     
       7. The symmetrical filter of  claim 1  wherein the pull down switch comprises a NMOS device. 
     
     
       8. The symmetrical filter of  claim 5  wherein the first resistor is approximately 25 kilo ohms. 
     
     
       9. The symmetrical filter of  claim 1  wherein the capacitor is approximately 50 pico Farads. 
     
     
       10. The voltage divider of  claim 5  wherein the first resistor has the same value as the second resistor. 
     
     
       11. A logic circuit for controlling a symmetrical filter, the symmetrical filter having an intermediate node, an input node for receiving an input signal, a supply node, a ground node, a pull up switch, a pull down switch, and an output node for providing an output signal, the logic circuit comprising: 
       a logic block coupled to the output node, the pull up switch, and the pull down switch; and  
       an inverter block coupled to the input node, the intermediate node and the logic block; and  
       the inverter block including:  
       a first inverter coupled between the input node and the intermediate node; and  
       a second inverter coupled between the intermediate node and the logic block.  
     
     
       12. The logic circuit of  claim 11  wherein the logic block comprises: 
       a NAND gate having a first input coupled to the inverter block, a second input coupled to the output node, and an output connected to the pull up switch; and  
       a NOR gate having a first input coupled to the inverter block, a second input coupled to the output node, and an output connected to the pull down switch.  
     
     
       13. The logic circuit of  claim 11  wherein the logic block comprises: 
       a NAND gate having a first input coupled to the second inverter, a second input coupled to the output node, and an output connected to the pull up switch: and  
       a NOR gate having a first input coupled to the second inverter, a second input coupled to the output node, and an output connected to the pull down switch.  
     
     
       14. The logic circuit of  claim 11 , further comprising: 
       a timing logic coupled to the logic block and wherein the timing logic comprises a plurality of flip-flops, the flip-flops being configured to delay the input signal received on the input node a predetermined number of clock cycles.  
     
     
       15. The logic circuit of  claim 11 , further comprising: 
       a first inverter coupled between the input node and the intermediate node;  
       a second inverter coupled between the intermediate node and the logic block;  
       a NAND gate having a first input coupled to the second inverter, a second input coupled to the output node, and an output connected to the pull up switch;  
       a NOR gate having a first input coupled to the second inverter, a second input coupled to the output node, and an output connected to the pull down switch; and  
       a timing logic coupled to the logic block, the timing logic including:  
       a plurality of flip-flops, the flip-flops being configured to delay the processing of the input signal received on the input node a predetermined number of clock cycles.  
     
     
       16. A symmetrical filter, comprising: 
       an input port for receiving a filter input signal;  
       a pull-up switch;  
       a pull-down switch;  
       a capacitor coupled to the pull-up and pull-down switches and the input port;  
       a comparator having a first input coupled to the pull-up and pull-down switches, and an output port for providing a filter output signal; and  
       control logic coupled to the pull-up switch and pull-down switches, the control logic controls the operation of the pull-up and pull-down switches in order to fully charge or fully discharge the capacitor.  
     
     
       17. A symmetrical filter, as defined in  claim 16 , wherein the pull-up switch is coupled to a supply voltage and the pull-down switch is coupled to ground.