Semiconductor device having a retrograde well structure and method of manufacturing thereof

Abstract

A semiconductor substrate is of a first conductivity type and has a retrograde well impurity concentration. A first of the first conductivity type and having a second impurity concentration with an impurity concentration peak is formed on a main surface of the semiconductor substrate. A first impurity layer of a third impurity concentration comes into contact with the underside of the retrograde well. The third impurity concentration is smaller than the impurity concentration peak of the first impurity concentration and the second impurity concentration. An element is formed on the retrograde well.

What is claimed is:  
     
       1. A semiconductor device comprising: 
       a semiconductor substrate of a first conductivity type and having a first impurity concentration,  
       a retrograde well of said first conductivity type and having a second impurity concentration with an impurity concentration peak, formed in a main surface of said semiconductor substrate,  
       a first impurity layer having a third impurity concentration in contact with the underside of said retrograde well being smaller in concentration than an impurity concentration peak of said first impurity concentration and the concentration peak of said second impurity concentration, and  
       an element formed on said retrograde well  
       wherein said element is a MOS type transistor, and  
       said semiconductor device further comprising a second impurity layer of a second conductivity type having a fourth impurity concentration and adjoining a third impurity layer of said first conductivity type having a fifth impurity concentration, said second and said third impurity layers being formed in another main surface of said semiconductor substrate, and  
       a CMOS transistor formed on at least said second and said third impurity layers for controlling said MOS type transistor.  
     
     
       2. The semiconductor device of  claim 1 , 
       wherein a fourth impurity layer of said first conductivity type is formed under at least said second and third impurity layers.  
     
     
       3. The semiconductor device of  claim 1 , 
       wherein said first impurity layer is of said second conductivity type.  
     
     
       4. The semiconductor device of  claim 1 , 
       wherein said impurity concentration peak of said second impurity concentration and an impurity concentration peak of said third impurity concentration are smaller in concentration than said impurity concentration peak of said first impurity concentration.  
     
     
       5. The semiconductor device of  claim 4 , 
       wherein a fifth impurity layer of said first conductivity type is formed under at least said second and third impurity layers.  
     
     
       6. The semiconductor device of  claim 4 , 
       wherein said first impurity layer is of said second conductivity type.  
     
     
       7. The semiconductor device of  claim 4 , 
       wherein said MOS type transistor is a transistor constituting a memory cell.  
     
     
       8. The semiconductor device of  claim 4 , 
       wherein said first impurity layer is formed more deeply than a separation insulation film formed in the main surface of said semiconductor substrate.  
     
     
       9. The semiconductor device of  claim 1 , 
       wherein said MOS type transistor is a transistor constituting a memory cell.  
     
     
       10. The semiconductor device of  claim 1 , 
       wherein said first impurity layer is formed more deeply than a separation insulation film formed in the main surface of said semiconductor substrate.  
     
     
       11. The semiconductor device of  claim 1 : 
       wherein said fifth impurity concentration has an impurity concentration peak, and said impurity concentration peak of said second impurity concentration and fifth impurity concentration are formed at roughly same depth position from the surface of said semiconductor substrate and having nearly same concentration.  
     
     
       12. The semiconductor device of  claim 11 : 
       wherein said impurity concentration peak of said second impurity concentration and said third impurity concentration are smaller in concentration than said impurity concentration peak of said first impurity concentration.  
     
     
       13. A semiconductor device comprising: 
       a semiconductor substrate of a first conductivity type and having a first impurity concentration,  
       a first impurity layer of said first conductivity type and having a second impurity concentration with an impurity concentration peak smaller than said first impurity concentration, formed in a main surface of said semiconductor substrate,  
       a second impurity layer of a second conductivity type and having a third impurity concentration with an impurity concentration peak smaller than said first impurity concentration, coming into contact with the underside of said first impurity layer, and  
       a MOS type transistor formed on said first impurity layer,  
       said semiconductor device further comprising a third impurity layer of said second conductivity type having a fourth impurity concentration adjoining a fourth impurity layer of said first conductivity type having a fifth impurity concentration, said third and said fourth impurity layers being formed in another main surface of said semiconductor substrate, and  
       a CMOS transistor formed on at least said third and said fourth impurity layers for controlling said MOS type transistor.  
     
     
       14. The semiconductor device of  claim 13 , 
       wherein a fifth impurity layer of said first conductivity type is formed under at least said third and fourth impurity layers.  
     
     
       15. The semiconductor device of  claim 13 , 
       wherein said MOS type transistor is a transistor constituting a memory cell.  
     
     
       16. The semiconductor device of  claim 13 , 
       wherein said second impurity layer is formed more deeply than a separation insulation film formed in the main surface of said semiconductor substrate.  
     
     
       17. The semiconductor device of  claim 13 , 
       wherein said third impurity concentration is lower than said second impurity concentration.  
     
     
       18. The semiconductor device of  claim 13 : 
       wherein said fifth impurity concentration has an impurity concentration peak, and said impurity concentration peak of said second impurity concentration and fifth impurity concentration are formed at roughly same depth position from the surface of said semiconductor substrate and having nearly same concentration.  
     
     
       19. A semiconductor device comprising: 
       a semiconductor substrate of a first conductivity type and having a first impurity concentration,  
       a first impurity layer having a second impurity concentration with an impurity concentration peak, formed in a main surface of said semiconductor substrate,  
       a second impurity layer having an impurity concentration peak of a third impurity concentration in contact with the underside of said first impurity layer, wherein said impurity concentration peak of said third impurity concentration is smaller than said first impurity concentration and said impurity concentration peak of said second impurity concentration,  
       a memory cell transistor formed in a main surface of said first impurity layer,  
       a third impurity layer having a fourth impurity concentration of a second conductivity type, formed in a main surface of said semiconductor substrate adjoining mutually other portions of said main surface of said semiconductor substrate,  
       a fourth impurity layer having a fifth impurity concentration of said first conductivity type, and  
       transistors of CMOS type formed at least in said third impurity layer and said fourth impurity layer.  
     
     
       20. The semiconductor device of  claim 19 , 
       further comprising a fifth impurity layer having said first conductivity type formed at least under said third impurity layer and said fourth impurity layer.  
     
     
       21. The semiconductor device of  claim 19 , 
       wherein said first impurity layer is of said second conductivity type.  
     
     
       22. The semiconductor device of  claim 19 , 
       wherein said second impurity layer is formed more deeply than a separation insulation film formed in the main surface of said semiconductor substrate.  
     
     
       23. The semiconductor device of  claim 19 , 
       wherein said impurity concentration peak of said second impurity concentration and said third impurity concentration are smaller in concentration than an impurity concentration peak of said first impurity concentration.  
     
     
       24. The semiconductor device of  claim 23 , 
       further comprising a fifth impurity layer having said first conductivity type formed at least under said third impurity layer and said fourth impurity layer.  
     
     
       25. The semiconductor device of  claim 23 , 
       wherein said first impurity layer is of said second conductivity type.  
     
     
       26. The semiconductor device of  claim 19 : 
       wherein said fifth impurity concentration has an impurity concentration peak, and said impurity concentration peak of said second impurity concentration and fifth impurity concentration are formed at roughly same depth position from the surface of said semiconductor substrate and having nearly same concentration.  
     
     
       27. The semiconductor device of  claim 26 : 
       wherein said impurity concentration peak of said second impurity concentration and third impurity concentration are smaller in concentration than said impurity concentration peak of said first impurity concentration.