On-line offset cancellation in flash A/D with interpolating comparator array

Abstract

A method for performing an auto-zero function in a flash analog to digital converter (“ADC”), the ADC including a reference voltage circuit, providing a plurality of evenly spaced analog reference voltages, and a plurality of system voltage comparators for comparing an input voltage against the reference voltages and providing an indication of which reference voltage corresponds to the input voltage. In the method the following steps are performed. A plurality of redundant voltage comparators are provided. A subset of the plurality of system voltage comparators are selected. Auto-zero is performed on the selected comparators, and the redundant comparators are used in the place of the selected comparators. The outputs of the main comparator array and the extra comparators are combined to produce a final digital output.

What is claimed is:  
     
       1. A method for performing an auto-zero function in a flash analog to digital converter (“ADC”), said ADC including a reference voltage circuit providing a plurality of evenly spaced analog reference voltages, a plurality of system voltage comparators for comparing an input voltage against said reference voltages and providing an indication of which reference voltage corresponds to said input voltage, comprising the following steps: 
       providing a plurality of redundant voltage comparators;  
       selecting a subset of said plurality of system voltage comparators;  
       performing auto-zero on said selected comparators; and  
       using said redundant comparators in the place of said selected comparators.  
     
     
       2. A method for performing an auto-zero function in a flash analog to digital converter (“ADC”), said ADC including a reference voltage circuit providing a plurality of evenly spaced analog reference voltages, a plurality of system voltage comparators for comparing an input voltage against said reference voltages and providing an indication of a one of said reference voltages of which said input voltage is below in level, comprising the following steps: 
       providing a plurality of redundant voltage comparators;  
       selecting a subset of said plurality of system voltage comparators;  
       performing auto-zero on said redundant voltage comparators;  
       performing auto-zero on said selected comparators; and  
       using said redundant comparators in the place of said selected comparators during a conversion operation.  
     
     
       3. A method for performing an auto-zero function in a flash analog to digital converter (“ADC”), and for performing an analog to digital conversion, said ADC having an input, said ADC including a reference voltage circuit providing a plurality of evenly spaced analog reference voltages, and said ADC including a plurality of system voltage comparators for comparing an input voltage against said reference voltages and providing an indication of a one of said reference voltages of which said input voltage is below in level, comprising the following steps: 
       applying an input voltage to said input;  
       providing a plurality of redundant voltage comparators;  
       selecting a subset of said plurality of system voltage comparators;  
       performing auto-zero on said redundant voltage comparators;  
       performing auto-zero on said selected comparators;  
       performing an analog to digital conversion on said input voltage using said redundant comparators in the place of said selected comparators; and  
       combining the outputs of said system voltage comparators and of said redundant comparators.  
     
     
       4. A method for performing an auto-zero function in a flash analog to digital converter (“ADC”), said ADC including a reference voltage circuit providing a plurality of evenly spaced analog reference voltages, a plurality of system voltage comparators for comparing an input voltage against said reference voltages and providing an indication signal representing an indication of which reference voltage corresponds to said input voltage, said indication signal being converted to a binary code corresponding to said input voltage, comprising the following steps: 
       providing a plurality of redundant voltage comparators;  
       selecting a subset of said plurality of system voltage comparators;  
       performing auto-zero on said redundant voltage comparators;  
       performing auto-zero on said selected comparators;  
       using said redundant comparators in the place of said selected comparators during a conversion operation;  
       converting the output of said system voltage comparators, less said selected comparators, to a first digital value;  
       converting the output of said redundant comparators to a second digital value; and  
       adding said first digital value and said second digital value.  
     
     
       5. A method for performing an auto-zero function in a flash analog to digital converter (“ADC”), said ADC including a reference voltage circuit providing a plurality of evenly spaced analog reference voltages, a plurality of system voltage comparators for comparing an input voltage against said reference voltages and providing a thermometer code corresponding to said input voltage, said thermometer code being provided to a converter for converting said thermometer code to a binary code corresponding to said input voltage, comprising the following steps: 
       providing a plurality of redundant voltage comparators;  
       selecting a subset of said plurality of system voltage comparators;  
       performing auto-zero on said redundant voltage comparators;  
       performing auto-zero on said selected comparators;  
       after a sufficient time has passed after said step of performing auto-zero on said redundant voltage comparators so that the outputs of said redundant voltage comparators becomes valid, using said redundant comparators in the place of said selected comparators during a conversion operation;  
       performing a thermometer code to binary code conversion on the output of said system voltage comparators, less said selected comparators, to generate a first digital value, wherein said outputs of said system voltage comparators, less said selected comparators, are concatenated by a shifting down of comparators above said selected comparators;  
       adding the outputs of said redundant comparators as binary values to generate a second binary digital value; and  
       adding said first digital value and said second digital value.