Counter logic for multiple memory configuration

Abstract

The present invention is an efficient system and method for flexible masking of output bits from a counter. The maskable counter system and method of the present invention modify the chain carry fed into a counter so that any bit (or bits) of the counter may be masked. A masked bit of a maskable counter system and method is utilized to facilitate user programmable control of multiple configurations in a memory. A maskable counter system comprises a mask register (e.g., a D flip flop), a counter (e.g., a D flip flop), and a masking coordination circuit. The masking coordination circuit permits a carry in signal, a carry out signal, and a counter output bit signal to operate in a normal incrementation manner if a mask bit is not asserted and prevents the counter output bit signal from changing if the mask bit is asserted.

What is claimed is:  
     
       1. A maskable counter system comprising: 
       a masking coordination circuit for permitting a counter output bit signal to operate in a normal incrementation manner if a mask bit is not asserted and prevents said counter output bit signal from incrementing if said mask bit is asserted;  
       a mask register for storing a mask bit that indicates whether a logical value of said counter output bit signal is prevented from incrementing or permitted to increment, said mask register coupled to said masking coordination circuit; and  
       a counter for providing said counter output bit signal, said counter coupled to said masking coordination circuit.  
     
     
       2. A maskable counter system of  claim 1  wherein said mask bit is asserted for any counter output bit in a counter output word and said counter output bit is masked. 
     
     
       3. A maskable counter system of  claim 1  wherein said mask bit is asserted for a least significant counter output bit in a counter output word and the counter output word is incremented by 2. 
     
     
       4. A maskable counter system of  claim 1  wherein said mask bit is asserted for a plurality of counter output bits in a counter output word and the counter output word is incremented by a power of 2. 
     
     
       5. A maskable counter system of  claim 1  wherein said masking coordination circuit comprises: 
       a local carry lookahead mask resolution circuit for providing an appropriate logical value for a local carry lookahead signal based upon resolving the logical value of said mask bit status and the logical value of said counter output bit signal from said counter;  
       a carry out circuit for providing an appropriate carry out signal based upon an analysis of the logical value of said local carry lookahead signal and the logical value of a carry in signal, said carry out circuit coupled to said local carry lookahead mask resolution circuit;  
       a mask coordination circuit for forwarding a carry in logical value unless a mask bit is asserted, said mask coordination circuit coupled to said carry out circuit; and  
       output mask coordination circuit for coordinating said mask coordination circuit and an output value from said counter from a previous cycle to provide an appropriate input logical value to said counter, said output mask coordination circuit coupled to said mask coordination circuit.  
     
     
       6. A maskable counter system of  claim 1  wherein said masking coordination circuit provides a carry out signal and a local carry lookahead signal that are utilized to generate a counter interrupt. 
     
     
       7. A maskable counter system of  claim 1  wherein said counter output bit is programmable when said mask bit is asserted. 
     
     
       8. A maskable counter system comprising: 
       a masking coordination circuit for permitting a counter output bit signal to operate in a normal incrementation manner if a mask bit is not asserted and prevents said counter output bit signal from incrementing if said mask bit is asserted;  
       a mask register for storing a mask bit that indicates whether a logical value of said counter output bit signal is prevented from incrementing or permitted to increment, said mask register coupled to said masking coordination circuit;  
       a counter for providing said counter output bit signal, said counter coupled to said masking coordination circuit; and  
       an option input for resetting said mask register and said counter, said option input coupled to said mask register and said counter register.  
     
     
       9. A maskable counter system of  claim 8  wherein said masking coordination circuit comprises: 
       a local carry lookahead mask resolution circuit for providing an appropriate logical value for a local carry lookahead signal based upon resolving the logical value of said mask bit status and the logical value of said counter output bit signal from said counter;  
       a carry out circuit for providing an appropriate carry out signal based upon an analysis of the logical value of said local carry lookahead signal and the logical value of a carry in signal, said carry out circuit coupled to said local carry lookahead mask resolution circuit;  
       a mask coordination circuit for forwarding a carry in logical value unless a mask bit is asserted, said mask coordination circuit coupled to said carry out circuit; and  
       output mask coordination circuit for coordinating said mask coordination circuit and an output value from said counter from a previous cycle to provide an appropriate input logical value to said counter, said output mask coordination circuit coupled to said mask coordination circuit.  
     
     
       10. A maskable counter system of  claim 8  wherein said masked bit is programmable by the user and is utilized to control a memory configuration multiplexer. 
     
     
       11. A maskable counter system of  claim 8  wherein said mask bit is asserted for any counter output bit in a counter output word and said counter output bit is masked. 
     
     
       12. A maskable counter system of  claim 8  wherein said mask bit is asserted for a least significant counter output bit in a counter output word and the counter output word is incremented by 2. 
     
     
       13. A maskable counter system of  claim 8  wherein said mask bit is asserted for a plurality of counter output bits in a counter output word and the counter output word is incremented by a power of 2. 
     
     
       14. A maskable counter system of  claim 8  wherein said mask bit is asserted for a counter output bit and said counter output bit is utilized to configure a memory depth or width. 
     
     
       15. A maskable counter method comprising the steps of: 
       permitting a carry in signal, a carry out signal, and a counter output bit signal to operate in a normal incrementation manner if a mask bit is asserted;  
       preventing said counter output bit signal from changing if said mask bit is not asserted; and  
       storing a mask bit.  
     
     
       16. The maskable counter method of  claim 15  further comprising the step masking any bit in a counter output word. 
     
     
       17. The maskable counter method of  claim 15  further comprising the step of utilizing a counter output word with maskable counter output bits to configure a memory. 
     
     
       18. The maskable counter method of  claim 15  further comprising the step of incrementing a counter bit value. 
     
     
       19. The maskable counter method of  claim 19  wherein said counter bit value is incremented by a power of 2. 
     
     
       20. The maskable counter method of  claim 15  further comprising the step of providing a carry ahead signal.