Loop stabilization technique in a phase locked loop (PLL) with amplitude compensation

Abstract

A phase locked loop circuit and method that substantially decouples control of the phase/frequency and the amplitude of the oscillation output such that the frequency of the oscillation can be controlled independently of the amplitude. The phase locked loop circuit comprises a phase/frequency control loop and an amplitude control loop wherein both loops control an oscillator that oscillates at a certain frequency in response to a phase/frequency control signal generated by the phase/frequency control loop. In addition, the oscillation amplitude is determined by an amplitude control signal generated by the amplitude control loop. As with conventional circuits of this type, a parasitic gain is coupled from the amplitude control loop into the phase/frequency control loop, thereby causing interference between the loops that leads to stability problems. To counter the coupling of the parasitic gain, an inverted gain is inserted from the amplitude control loop into the phase/frequency control loop in opposite to the parasitic gain, so as to effectively cancel the interference. The circuit and method also provide for canceling the opposite parasitic gain that is coupled from the phase/frequency loop into the amplitude control loop.

What is claimed is:  
     
       1. A method for stabilizing a phase/frequency control loop in the presence of an amplitude control loop in a phase locked loop circuit, comprising: 
       determining a first parasitic gain that is coupled from the amplitude control loop into the phase/frequency control loop; and  
       inserting a first inverse gain into the phase/frequency control loop that is substantially equal to the first parasitic gain and opposite thereto to cancel the effect of the first parasitic gain by summing a scaled amount of an amplitude control current used to control the amplitude control loop into a phase/frequency control current used to control the phase/frequency control loop.  
     
     
       2. The method of  claim 1 , wherein the phase locked loop circuit includes a gm (transconductance)-C relaxation-type oscillator that is common to both of the phase/frequency and amplitude control loops. 
     
     
       3. The method of  claim 2 , wherein the gm-C relaxation-type oscillator comprises two cascaded gm stages that provide 180 degrees of phase shift. 
     
     
       4. The method of  claim 3 , wherein the phase locked loop circuit has an oscillation cycle and produces an oscillation having an amplitude, and wherein each gm stage is loaded with a net negative gm circuit that produces a net negative amount of transconductance at its output to compensate for resistive losses, initiate the oscillation cycle, and set the oscillation amplitude. 
     
     
       5. The method of  claim 4 , wherein each net negative gm circuit comprises m source-coupled cross-connected differential pairs with resistive loads in parallel with n source coupled diode-connected differential pairs with resistive loads, wherein m>n. 
     
     
       6. The method of  claim 5 , wherein the resistive loads are produced by saturated PMOS transistors. 
     
     
       7. The method of  claim 1 , further comprising: 
       determining a second parasitic gain that is coupled from the phase/frequency control loop into the amplitude control loop; and  
       inserting a second inverse gain into the amplitude control loop that is substantially equal the second parasitic gain and opposite thereto to cancel the effect of the second parasitic gain.  
     
     
       8. The method of  claim 7 , wherein the phase/frequency control loop is primarily controlled as a function of a phase/frequency control current and the amplitude control loop is primarily controlled as a function of an amplitude control current, and further wherein the second inverse gain is produced by summing a scaled amount of the phase/frequency control current into the amplitude control current. 
     
     
       9. A phase locked loop circuit comprising: 
       a phase/frequency control loop including a gm (transconductance)-C relaxation-type oscillator that produces an output signal having a frequency corresponding to a frequency control signal;  
       an amplitude control loop including the gm-C relaxation-type oscillator such that the output signal has an amplitude corresponding to an amplitude control signal, said amplitude control loop coupling a parasitic gain into the phase/frequency control loop and providing an inverted gain in opposite to the parasitic gain to the phase/frequency control loop to substantially cancel the effect of the parasitic gain such that control of the phase/frequency of the phased locked loop circuit is decoupled from control of the amplitude of the phase locked loop circuit.  
     
     
       10. The phase locked loop circuit of  claim 9 , wherein the gm-C relaxation-type oscillator comprises two cascaded gm stages that provide 180 degrees of phase shift. 
     
     
       11. The phase locked loop circuit of  claim 9 , wherein the phase locked loop circuit has an oscillation cycle and produces an oscillation having an amplitude, and wherein each gm stage is loaded with a net negative gm circuit that produces a net negative amount of transconductance at its output to compensate for resistive losses, initiate the oscillation cycle, and set the oscillation amplitude. 
     
     
       12. The phase locked loop circuit of  claim 11 , wherein each net negative gm circuit comprises m source-coupled cross-connected differential pairs with resistive loads in parallel with n source coupled diode-connected differential pairs with resistive loads, wherein m>n. 
     
     
       13. The phase locked loop circuit of  claim 12 , wherein the resistive loads are produced by saturated PMOS transistors. 
     
     
       14. A phase locked loop circuit comprising: 
       a phase/frequency control loop including:  
       a phase detector;  
       an integrator;  
       a first loop filter;  
       a first voltage to current converter; and  
       a current-controlled oscillator; and  
       an amplitude control loop including:  
       a peak detector/comparator;  
       a second loop filter;  
       a second voltage-to-current converter; and  
       the current-controlled oscillator,  
       wherein a parasitic gain is coupled from the amplitude control loop into the phase/frequency control loop and an inverted gain is inserted into the phase/frequency control loop opposite to the parasitic gain to substantially cancel the effect of the parasitic gain such that control of the phase/frequency control loop is decoupled from the amplitude control loop.  
     
     
       15. The circuit of  claim 14 , wherein the parasitic gain comprises a parasitic current coupled from the amplitude control loop into the phase/frequency control loop, and the current-controlled oscillator comprises: 
       a first transconductance (gm) stage having an input and output;  
       a second gm stage connected to the output of the first gm stage;  
       an inverter, having an input connected to the output of the second gm stage and an output connected to the input of the first gm stage to form a feedback loop;  
       a first net negative gm circuit connected to the output of the first gm stage; and  
       a second net negative gm circuit connected to the output of the second gm stage.  
     
     
       16. The circuit of  claim 13 , wherein each of the first and second net negative gm circuits comprise m source-coupled cross-connected differential pairs with resistive loads in parallel with n source coupled diode-connected differential pairs with resistive loads, wherein m>n. 
     
     
       17. The circuit of  claim 14 , wherein the resistive loads are produced by saturated PMOS transistors.