Method for fabricating semiconductor device

Abstract

The present invention discloses a method for fabricating a semiconductor device. A protective film for protecting a device isolation film is formed on the device isolation film for the contact hole formation process, thereby preventing a device isolation film from being damaged due to misalignment in a lithography process or overetch during the etch process. Accordingly, gate induced drain leakage current is not generated, contact junction leakage current is reduced, and the contact properties are improved. Improvements in the contact properties produce corresponding improvements in the properties and yield of the semiconductor devices manufactured according to the invention.

What is claimed is:  
     
       1. A method of forming a contact hole in a semiconductor device according to a self-aligned contact process comprising, in the following order, the steps of: 
       forming an insulation film pattern on a semiconductor substrate that exposes a device isolation region of the semiconductor substrate;  
       forming a trench by etching the device isolation region using the insulation film pattern as an etching mask;  
       forming an insulation film over the resulting structure;  
       performing a chemical mechanical polishing process to expose the insulation film pattern;  
       etching the insulation layer using a wet etch process to form a device isolation film in the trench, the surface of the device isolation film being lower then that of the semiconductor substrate;  
       forming a protective film over the resultant structure;  
       removing the protective film and the insulation film pattern by a chemical mechanical polishing process using the protective film over the device isolation film as a process endpoint to form a protective film pattern on the surface of the device isolation film;  
       removing the remaining portion of the insulation film pattern;  
       forming a stacked structure comprising a gate insulation film, a gate electrode pattern, and a mask insulation film pattern in the active region of the semiconductor substrate, the stacked structure having an insulation film spacer at its sidewalls;  
       forming a planarization film over the resulting structure; and  
       etching the planarization film to expose the predetermined regions of the active region, thereby forming contact holes.  
     
     
       2. The method according to  claim 1 , wherein the insulation film pattern has a stacked structure comprising a pad oxide film pattern and a nitride film pattern. 
     
     
       3. The method according to  claim 1 , wherein the protective film formed from one or more materials selected from the group consisting of SiN, SiON, Al 2 O 3 , Ta 2 O 5 , SiOCH, and SiCH. 
     
     
       4. The method according to  claim 1 , wherein the wet etch process utilizes a mixed solution of HF and deionized water or a mixed solution of HF, deionized water and NH 4 OH. 
     
     
       5. The method according to  claim 2 , wherein the nitride film pattern is removed using a wet etch process utilizing a mixed solution of H 3 PO 4  and deionized water. 
     
     
       6. The method according to  claim 2 , wherein the nitride film pattern is removed using an isotropic dry etching process under a mixed gas, the mixed gas comprising a fluorine-containing gas, an oxygen-containing gas and an inert gas. 
     
     
       7. The method according to  claim 1 , wherein the mask insulation film pattern consists of a SiON film or a SRON film. 
     
     
       8. The method according to  claim 1  or  7 , wherein the mask insulation film pattern is etched with a mixed gas to form a vertical profile, the mixed gas comprising a mixture of CF 4 , O 2  and Ar or a mixture of CHF 3 , O 2  and Ar. 
     
     
       9. The method according to  claim 1 , wherein the planarization film is etched under an etch gas, the etch gas comprising a perfluorocarbon-containing gas, the perfluorocarbon-containing gas comprising at least one gas selected from the group consisting of C 2 F 6 , C 2 F 4 , C 3 F 6 , C 3 F 8 , C 4 F 6 , C 4 F 8 , C 5 F 8 , C 5 F 10 , and C 2 HF 5 . 
     
     
       10. The method according to  claim 9 , wherein the planarization film is etched using a mixed gas, the mixed gas comprising a perfluorocarbon-containing gas and a hydrogen-containing gas, in order to increase an etching selection ratio and prevent the occurrence of etch stop phenomenon. 
     
     
       11. The method according to  claim 10 , wherein the hydrogen-containing gas comprises one or more gases selected from the group consisting of CHF 3 , CH 3 F, CH 2 F 2 , CH 2 , CH 4 , C 2 H 4 , and H 2 . 
     
     
       12. The method according to  claim 1 , wherein the planarization film is etched under an etch gas, the etch gas comprising a gas having the composition C x H y F z  where x, y, and z are each at least 2. 
     
     
       13. The method according to  claim 1 ,  9  or  12 , wherein the etch gas further comprises an inert gas.