Semiconductor integrated circuit device

Abstract

Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

What is claimed is:  
     
       1. A semiconductor integrated circuit device comprising: 
       an active region and a dummy region of a semiconductor substrate;  
       a semiconductor element formed in said active region;  
       a trench defining said active region and dummy region;  
       an element isolation insulating film having said trench embedded with an insulating film including a film planarized by polishing; and  
       an element isolation region defining said active region and being comprised of said dummy region and element isolation insulating film,  
       a distance between said dummy region and said active region being not greater than twice the depth of said trench.  
     
     
       2. A semiconductor integrated circuit device comprising: 
       an active region and a dummy region of a semiconductor substrate;  
       a semiconductor element formed in said active region;  
       a trench defining said active region and dummy region;  
       an element isolation insulating film having said trench embedded with an insulating film including a film planarized by polishing; and  
       an element isolation region defining said active region and being comprised of said dummy region and element isolation insulating film,  
       said dummy region having a width at least twice a minimum line width.  
     
     
       3. A semiconductor integrated circuit device comprising: 
       interconnections each formed on a principal surface of a semiconductor substrate;  
       dummy interconnections each formed of an interconnection layer same with that of said interconnections and disposed in a region spaced from said interconnections; and  
       an insulating film covering said interconnections and dummy interconnections and including a film planarized by polishing,  
       a distance between adjacent members of said dummy interconnections and said interconnections being not greater than twice a height of said interconnections, and  
       said dummy interconnections each having no electrical connection with elements.  
     
     
       4. A device according to  claim 3 , wherein said dummy interconnections are formed also in a scribing area. 
     
     
       5. A device according to  claim 3 , wherein said dummy interconnections are not formed, in the same interconnection layer with that of a bonding pad portion or a marker portion for photolithography, at a periphery of said bonding pad portion or marker portion. 
     
     
       6. A device according to  claim 3 , wherein in a region of at least 95% of a chip, a pattern distance between adjacent patterns of said interconnections and said dummy interconnections is not greater than twice a height of said interconnections; and in a region not greater than 5% of said chip, said distance is not greater than 4 times the height of said interconnections. 
     
     
       7. A device according to  claim 3 , wherein each interconnection constitutes a bit line of a DRAM. 
     
     
       8. A semiconductor integrated circuit device comprising: 
       interconnections formed on a principal surface of a semiconductor substrate;  
       dummy interconnections each formed of a same interconnection layer with that of said interconnections and disposed in a region spaced from said interconnections; and  
       an insulating film covering said interconnections and dummy interconnections and including a film planarized by polishing,  
       a length of said dummy interconnections being larger than a width of said dummy interconnections,  
       the length of said dummy interconnections being not less than twice a minimum line width; and  
       said dummy interconnections each having no connection with elements.  
     
     
       9. A semiconductor integrated circuit device comprising: 
       interconnections formed on a principal surface of a semiconductor substrate;  
       dummy interconnections each formed of a same interconnection layer with that of said interconnections and disposed in a region spaced from said interconnections; and  
       an insulating film covering said interconnections and dummy interconnections and including a film planarized by CMP method,  
       said dummy interconnections each being not formed, in the same interconnection layer with that of a bonding pad portion or a marker portion for photolithography, at peripheries of said bonding pad portion or marker portion.