Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device has a diffusion layer formed on a silicon substrate, an interlayer insulator which covers a surface of the silicon substrate and whose surface is planarized, and a dielectric capacitor composed of a lower electrode connected to the diffusion layer via a buried conductive layer which is buried within a contact hole opened in the interlayer insulator and which is formed of a barrier metal layer composed of a contact plug, a low resistance layer and tantalum silicon nitride, and a dielectric film formed on the lower electrode, and an upper electrode. The lower electrode has a side-wall sloped configuration that its cross-sectional area monotonously increases from the buried conductive layer side toward the. upper dielectric film. Thus, a high-integration semiconductor device which allows the lower electrode to be micro-fabricated and enables lower-voltage operation and higher reliability can be obtained.

What is claimed is:  
     
       1. A semiconductor device comprising: 
       a diffusion layer formed on a semiconductor substrate;  
       an interlayer insulator which covers a surface of the semiconductor substrate and whose surface is planarized; and  
       a dielectric capacitor comprising a lower electrode connected to the diffusion layer via a buried conductive layer which is buried within a contact hole opened in the interlayer insulator, the buried conductive layer in the contact hole including a lower plug member and an upper barrier layer,  
       a dielectric film formed on the lower electrode, and an upper electrode formed on the dielectric film,  
       wherein the lower electrode has a flat upper surface and a side-wall sloped configuration such that a cross-sectional area of the lower electrode is greater at the flat upper surface of the lower electrode than at a lower surface of the lower electrode adjacent the buried conductive layer.  
     
     
       2. A semiconductor device having a memory cell which comprises: 
       an insulated-gate field-effect transistor including a gate insulator, a gate electrode and a pair of diffusion layers formed on a semiconductor substrate;  
       an interlayer insulator which covers surfaces of the insulated-gate field-effect transistor and the semiconductor substrate and whose surface is planarized;  
       a dielectric capacitor comprising a lower electrode connected to one of the diffusion layers of the insulated-gate field-effect transistor via a buried conductive layer which is buried within a contact hole opened in the interlayer insulator, the buried conductive layer including a lower plug member and an upper barrier layer, a dielectric film formed on the lower electrode, and an upper electrode formed on the dielectric film,  
       wherein the lower electrode has a flat entire upper surface and a side-wall sloped configuration so that a cross-sectional area of the lower electrode is greater at the flat upper surface of the lower electrode than at a lower surface of the lower electrode adjacent the buried conductive layer.  
     
     
       3. The semiconductor device according to  claim 1 , further comprising a second insulating film which covers a side wall of the lower electrode, a surface of the second insulating film being planarized and further flush with a surface of the lower electrode, wherein the dielectric film is formed so as to cover at least an entire top surface of the lower electrode and the upper electrode is placed on top of the dielectric film. 
     
     
       4. The semiconductor device according to  claim 1 , wherein the upper barrier layer is made of tantalum silicon nitride. 
     
     
       5. The semiconductor device according to  claim 1 , wherein the dielectric film is a ferroelectric film. 
     
     
       6. A method for manufacturing a semiconductor device comprising a diffusion layer formed on a semiconductor substrate; an interlayer insulator which covers a surface of the semiconductor substrate; and a dielectric capacitor comprising a lower electrode connected to the diffusion layer via a buried conductive layer which is buried within a contact hole opened in the interlayer insulator, the buried conductive layer in the contact hole including a lower plug member and an upper barrier layer, a dielectric film formed on the lower electrode, and an upper electrode formed on the dielectric film, wherein the lower electrode has a flat upper surface and a side-wall sloped configuration such that a cross-sectional area of the lower electrode is greater at the flat upper surface of the lower electrode than at a lower surface of the lower electrode adjacent the buried conductive layer; the method comprising: 
       forming the diffusion layer on the semiconductor substrate;  
       forming on the semiconductor substrate the interlayer insulator having a surface planarized;  
       forming in the interlayer insulator a contact hole extending to the diffusion layer;  
       burying and forming within the contact hole the buried conductive layer including the lower plug member and the upper barrier layer;  
       depositing a second insulating film on a surface of the semiconductor substrate including the interlayer insulator and the buried conductive layer;  
       forming in the second insulating film a contact hole having a slope-shaped side wall and having a cross-sectional area which decreases from a surface of the second insulating film toward the buried conductive layer so that a surface of the buried conductive layer and its peripheral part are exposed;  
       forming a lower-electrode-forming conductor thin film on the second insulating film, the interlayer insulator and the buried conductive layer;  
       forming the lower electrode by planarizing the lower-electrode-forming conductor thin film so that the surface of the second insulating film is exposed and so that a flat upper surface of the lower electrode-forming conductor thin film becomes flush with the surface of the second insulating film; and  
       forming the upper electrode and the capacitor dielectric film by sequentially stacking a capacitor-dielectric-film-forming dielectric thin film and an upper-electrode-forming conductor thin film on the lower electrode and the second insulating film and by patterning the upper-electrode-forming conductor thin film and the capacitor-dielectric-film-forming dielectric thin film so that the capacitor dielectric film completely covers a surface of the lower electrode.  
     
     
       7. A method for manufacturing a semiconductor device comprising an insulated-gate field-effect transistor including a gate insulator, a gate electrode and a pair of diffusion layers formed on a semiconductor substrate; an interlayer insulator which covers surfaces of the insulated-gate field-effect transistor and the semiconductor substrate and whose surface is planarized; a dielectric capacitor comprising a lower electrode connected to one of the diffusion layers of the insulated-gate field-effect transistor via a buried conductive layer which is buried within a contact hole opened in the interlayer insulator, the buried conductive layer including a lower plug member and an upper barrier layer, a dielectric film formed on the lower electrode, and an upper electrode formed on the dielectric film, wherein the lower electrode has a flat entire upper surface and a side-wall sloped configuration so that a cross-sectional area of the lower electrode is greater at the flat upper surface of the lower electrode than at a lower surface of the lower electrode adjacent the buried conductive layer; the method comprising: 
       forming on the semiconductor substrate the insulated-gate field-effect transistor having the gate insulator, the gate electrode and the pair of diffusion layers;  
       forming on the insulated-gate field-effect transistor and the semiconductor substrate the interlayer insulator having a surface planarized;  
       forming in the interlayer insulator a contact hole extending to one of the diffusion layers of the insulated-gate field-effect transistor;  
       burying and forming within the contact hole the buried conductive layer including the lower plug member and the upper barrier layer;  
       depositing a second insulating film;  
       forming in the second insulating film a contact hole having a slope-shaped side wall and having a cross-sectional area which decreases from a surface of the second insulating film toward the buried conductive layer so that a surface of the buried conductive layer and its peripheral part are exposed;  
       forming a lower-electrode-forming conductor thin film on the second insulating film, the interlayer insulator and the buried conductive layer;  
       forming the lower electrode by planarizing the lower-electrode-forming conductor thin film so that the surface of the second insulating film is exposed and so that a surface of the lower electrode-forming conductor thin film becomes flush with the surface of the second insulating film; and  
       forming the upper electrode and the capacitor dielectric film by sequentially stacking a capacitor-dielectric-film-forming dielectric thin film and an upper-electrode-forming conductor thin film on the lower electrode and the second insulating film and by patterning the upper-electrode-forming conductor thin film and the capacitor-dielectric-film-forming dielectric thin film so that the capacitor dielectric film completely covers the flat upper surface of the lower electrode.  
     
     
       8. The method for manufacturing a semiconductor device according to  claim 6 , wherein removal of the surface of the buried conductive layer and the second insulating film on its peripheral part is performed by wet etching process. 
     
     
       9. The method for manufacturing a semiconductor device according to  claim 6 , wherein the step of forming the lower electrode by planarizing the lower-electrode-forming conductor thin film so that the surface of the second insulating film is exposed and so that a surface of the lower electrode-forming conductor thin film becomes flush with the surface of the second insulating film is performed by chemical mechanical polishing process. 
     
     
       10. A semiconductor device comprising: 
       a diffusion layer supported by a semiconductor substrate;  
       an interlayer insulator supported by the semiconductor substrate; and  
       a dielectric capacitor comprising a lower electrode connected to the diffusion layer via a buried conductive layer which is buried within a contact hole in the interlayer insulator, the buried conductive layer in the contact hole including a lower plug member and a barrier layer,  
       a dielectric film formed on the lower electrode, and an upper electrode of the capacitor formed on the dielectric film,  
       wherein the lower electrode of the capacitor has a flat upper surface and a side-wall sloped configuration such that a cross-sectional area of the lower electrode is greater at the flat upper surface of the lower electrode than at a lower surface of the lower electrode adjacent the buried conductive layer.