Multiphase clock generator

Abstract

The Sync State outputs are used in combination with the multiple phase outputs to generate and error signal which is operable to generate a control voltage which controls the frequency of the MVCO and to-generate a shifted clock which is divided in a sequential circuit to generate the quadrature clock with a frequency F.

What is claimed is:  
     
       1. An apparatus for generating K-phases of a multiple phase clock (MPCK), said MPCK having a frequency F corresponding to a reference clock of frequency F, said apparatus comprising: 
       a voltage controlled oscillator: with M-phase outputs (MPVCO), said M-phase outputs having frequency J set in response to a control voltage;  
       an M-phase detector (MPD) receiving said reference clock and said M-phase outputs of said MPVCO, said MPD generating M-detector outputs in response to said M-phase outputs and said reference clock;  
       a Sync State logic circuit receiving said M-detector outputs of said MPD, said Sync State logic circuit generating a Sync State output and an error signal, said error signal processed by a citcuit to generate said control voltage for said MPVCO; and  
       a multiple phase clock logic circuit (MPCL) receiving said M-phase outputs of said MPVCO, said MPCL generating said K-phases of said MPCK.  
     
     
       2. The apparatus of  claim 1 , wherein said frequency J is greater than said frequency F but less than a frequency 3 F. 
     
     
       3. The apparatus of  claim 1 , wherein said frequency J is greater than said frequency F but less than a frequency 3 F and nominally a frequency 2 F. 
     
     
       4. The apparatus of  claim 1 , wherein said error signal is generated in response to said Sync State output and one of said M-phase outputs. 
     
     
       5. The apparatus of  claim 1 , wherein said MPCL comprises K/2 first and K/2 second sequential logic gates, each of said first sequential logic gates receiving a selected first M-phase output and generating a first phase of said K-phases and said second sequential logic gate receiving said first M-phase output and generating a second phase of said K-phases. 
     
     
       6. The apparatus of  claim 5 , wherein each of said first sequential logic gates is a positive going edge triggered (P) D-Type flip flop (FF), said PD-Type FF having a data input, a clock input, an output and an inverting output, said data input of said PD-Type FF coupled to said inverting output, said clock input coupled to said selected first M-phase output, and said output generating said first phase of said K-phases. 
     
     
       7. The apparatus of  claim 5 , wherein each of said second sequential logic gate is a negative going edge triggered (N) D-Type flip flop (FF), said ND-Type FF having a data input, a clock input, an output and an inverting output, said data input of said ND-Type FF coupled to said inverting output, said clock input coupled to said selected first M-phase output, and said output generating said second phase of said K-phases. 
     
     
       8. The apparatus of  claim 1 , wherein M is equal to five. 
     
     
       9. The apparatus of  claim 1 , wherein K is equal to twenty. 
     
     
       10. The apparatus of  claim 1 , wherein said frequency J is equal to a frequency 2 F in a steady state condition. 
     
     
       11. An integrated circuit (IC) for generating K-phases of a multiple phase clock (MPCK), said MPCK having a frequency F corresponding to a reference clock of frequency F, said IC comprising: 
       a voltage controlled oscillator with M-phase outputs (MPVCO), said M-phase outputs having frequency J set in response to a control voltage;  
       an M-phase detector (MPD) receiving said reference clock and said M-phase outputs of said MPVCO, said MPD generating M-detector outputs in response to said M-phase outputs and said reference clock;  
       a Sync State logic circuit receiving said M-detector outputs of said MPD, said Sync State, logic circuit generating a Sync State output and an error signal, said error signal processed by a circuit to generate said control voltage for said MPVCO; and  
       a multiple phase clock logic circuit (MPCL) receiving said M-phase outputs of said MPVCO, said MPCL generating said K-phases of said MPCK.  
     
     
       12. The apparatus of  claim 11 , wherein said frequency J is greater than said frequency F but less than a frequency 3 F. 
     
     
       13. The IC of  claim 11 , wherein said frequency J is greater than said frequency F but less than a frequency 3 F and nominally a frequency 2 F. 
     
     
       14. The IC of  claim 11 , wherein said error signal is generated in response to said Sync State output and one of said M-phase outputs. 
     
     
       15. The IC of  claim 11 , wherein said MPCL comprises K/2 first and K/2 second sequential logic gates, each of said first sequential logic gates receiving a selected first M-phase output and generating a first phase of said K-phases and said second sequential logic gate receiving said first M-phase output and generating a second phase of said K-phases. 
     
     
       16. The IC of  claim 15 , wherein each of said first sequential logic gates is a positive going edge triggered (P) D-Type flip flop (FF), said PD-Type FF having a data input, a clock input, an output and an inverting output, said data input of said PD-Type FF coupled to said inverting output, said clock input coupled to said selected first M-phase output, and said output generating said first phase of said K-phases. 
     
     
       17. The IC of  claim 15 , wherein each of said second sequential logic gates a negative going edge triggered (N) D-Type flip flop (FF), said ND-Type FF having a data input, a clock input, an output and an inverting output, said data input of said ND-Type FF coupled to said inverting output, said clock input coupled to said selected first M-phase output, and said output generating said second phase of said K-phases. 
     
     
       18. The IC of  claim 11 , wherein M is equal to five. 
     
     
       19. The IC of  claim 11 , wherein K is equal to twenty. 
     
     
       20. The IC of  claim 11 , wherein said frequency J is equal to a frequency 2 F in a steady state condition. 
     
     
       21. A method for generating K-phases of a multiple phased clock (MPCK), said MPCK having a frequency F corresponding to a reference clock of frequency F, said method comprising the steps of: 
       generating in a multiple phased output voltage controlled oscillator (MPVCO) M-phases of a frequency J equal to F×N set in response to a control voltage wherein N is greater than one;  
       sampling and latching states of said M-phase outputs of said MPVCO with edges of said reference clock generating sampled phase outputs;  
       generating M-detector outputs in response to said sampled phase outputs and said reference clock;  
       generating a Sync State output by combining in a logic circuit selected ones of said M-detector outputs;  
       generating an error signal in response to said Sync State output, said error signal processed to generate said control voltage for said MPVCO; and  
       generating said K-phases of said reference clock by dividing said M-phase outputs in sequential logic gates.  
     
     
       22. The method of  claim 21 , wherein said frequency J is greater than said frequency F but less than a frequency 3 F. 
     
     
       23. The method of  claim 21 , wherein said frequency J is greater than said frequency F but less than a frequency 3 F and nominally a frequency 2 F. 
     
     
       24. The method of  claim 21 , wherein said error signal is generated in response to said Sync State output and one of said M-phase outputs, said error signal operable to generate a control input voltage to said MPVCO, said frequency J of said MPVCO proportional to said control input voltage. 
     
     
       25. The method of  claim 21 , wherein said sequential logic gates comprise K/2 first and K/2 second sequential logic gates, each of said first sequential logic gates receiving a selected first M-phase output and generating a first phase of said K-phases and said second sequential logic gate receiving said first M-phase output and generating a second phase of said K-phases. 
     
     
       26. The method of  claim 25 , wherein each of said first sequential logic gates is a positive going edge triggered (P) D-Type flip flop (FF), said PD-Type FF having a data input, a clock input, an output and an inverting output, said data input of said PD-Type FF coupled to said inverting output, said clock input coupled to said selected first M-phase output, and said output generating said first phase of said K-phases. 
     
     
       27. The method of  claim 25 , wherein each of said second sequential logic gates is a negative going edge triggered (N) D-Type flip flop (FF), said ND-Type FF having a data input, a clock input, an output and an inverting output, said data input of said ND-Type FF coupled to said inverting output, said clock input coupled to said selected first M-phase output, and said output generating said second phase of said K-phases. 
     
     
       28. The method of  claim 21 , wherein M is equal to five. 
     
     
       29. The method of  claim 21 , wherein K is equal to twenty. 
     
     
       30. The method of  claim 21 , wherein said frequency J is equal to a frequency 2 F in a steady state condition.