Two modes for executing branch instructions of different lengths and use of branch control instruction and register set loaded with target instructions

Abstract

A processor and accompanying program are disclosed which utilize branch control instructions in cooperation with branch instructions to reduce branch latency. The branch control instruction and branch instruction have a format/structure that is designed to execute flexibly and efficiently by making use of separate dedicated target address and target branch instruction register sets used by a pipeline within the processor.

What is claimed is:  
     
       1. A processor comprising: 
       a plurality of dedicated address registers for storing a plurality of different branch target addresses; and  
       an instruction decoder decoding an instruction supplied thereto and providing control signals according to results of said decoding; and  
       an execution unit responsive to the control signals and executing said instruction; wherein said instruction can include:  
       1) a first instruction including an operation code field defining a branch control operation; and an address field used for calculating a branch target address for a branch, and a first register selection field for specifying one of said plurality of dedicated address registers in which said branch target address is to be stored after it is calculated; and  
       2) a second instruction including an operation code field defining a branch operation, a second register selection field for specifying one of said plurality of dedicated address registers that stores said branch target address to be used for the branch operation, and a branch condition field for specifying a branch condition to be evaluated in determining whether said branch should be taken;  
       wherein said second instruction includes a first length instruction n bits in length, and a second length instruction whose length is 2n bits; and  
       wherein execution by the processor of said first instruction and said second instruction is arranged so as to reduce latency for handling said branch operation, and such that resolution of said branch condition is performed during execution of said second instruction; and  
       further wherein the microprocessor operates with a first mode for executing said first length instruction and a second mode for executing said second length instruction.  
     
     
       2. A microprocessor according to  claim 1 , further including a program counter (PC), wherein said address field of said first instruction further includes a field for immediate data and wherein said branch target address to be stored in one of said plurality of dedicated address registers defined by said first register selection field is calculated by adding said immediate data to contents of said program counter. 
     
     
       3. A microprocessor according to  claim 1 , further including a plurality of general purpose registers, wherein said first instruction further includes a source register selection field for specifying one of said plurality of general registers, and wherein data in said one of the general registers specified by the source register selection field is stored in one of said plurality of dedicated address registers defined by said first register selection field as said branch target address. 
     
     
       4. A microprocessor according to  claim 1  further including: 
       a program counter (PC), and  
       a plurality of general purpose registers;  
       wherein said first instruction further includes a source register selection field for specifying one of said plurality of general registers, and wherein said branch target address to be stored in one of said plurality of dedicated address registers defined by said first register selection field is calculated by adding contents of the program counter (PC) to data in said one of said general registers specified by said source register selection field.  
     
     
       5. A microprocessor according to  claim 1 , wherein said first instruction further includes a field for indicating that instruction execution flow is likely to pass to said second instruction. 
     
     
       6. A microprocessor according to  claim 1 , wherein said plurality of dedicated address registers store virtual addresses. 
     
     
       7. A microprocessor according to  claim 1 , wherein the microprocessor further includes an instruction buffer for storing an instruction pointed to by said branch target address. 
     
     
       8. A microprocessor according to  claim 1 , wherein said plurality of dedicated address registers number at least 8. 
     
     
       9. A microprocessor according to  claim 1 , wherein said first register selection field is at least 3 bits in length. 
     
     
       10. A microprocessor according to  claim 1 , further comprising: a program counter, wherein said second instruction causes said branch target address held in one of said plurality of dedicated address registers specified by said second register selection field to be loaded into said program counter. 
     
     
       11. A microprocessor according to  claim 1 , further comprising: 
       a program counter (PC); and  
       plurality of general purpose registers;  
       wherein said second instruction further includes:  
       a first general register selection field specifying one of said plurality of general registers, and  
       a second general register selection field specifying one of said plurality of general registers, and wherein said second instruction causes said branch target address held in one of said plurality of dedicated address registers specified by said second register selection field to be loaded into said program counter (PC) in accordance with a result of comparing a value of said general register specified by said first general register selection field with a value of said general register specified by said second general register selection field.  
     
     
       12. A microprocessor according to  claim 1 , further comprising: 
       a program counter (PC); and  
       a plurality of general registers; and  
       wherein said second instruction further includes:  
       a first general register selection field specifying one of said plurality of general registers, and  
       an immediate data field for indicating a displacement value to be used in calculating said branch target address, and wherein said second instruction causes said branch target address held in one of said plurality of dedicated address registers specified by a second register selection field to be loaded into said program counter (PC) in accordance with a result of comparing a value of said general register specified by said first general register selection field with a value of said general register specified by said second general register selection field.  
     
     
       13. A microprocessor according to  claim 1 , wherein said second register selection field is at least 3 bits in length. 
     
     
       14. A microprocessor according to  claim 1 , wherein both said first and said second instruction are at least 32-bits in length. 
     
     
       15. A computer program adapted to be executed on a computing machine having a first loadable dedicated register set for storing a plurality of branch target instruction addresses, and a second loadable dedicated register set for storing a plurality of branch target instructions, the computer program comprising: 
       a set of instructions adapted to be executed on the computing machine, said instructions including:  
       1) a first instruction including an operation code field defining a branch control operation, and an address field used for calculating a branch target address for a program branch, and a first register selection field for specifying a register in the first loadable dedicated register set for storing said branch target address as one of the plurality of branch target instruction addresses; and  
       2) a second instruction including an operation code field defining a program branch, and a second register selection field for identifying said register in the first loadable dedicated register set so that said branch target address can be read from such register and used to locate a branch target instruction from the plurality of branch target instructions stored in the second loadable dedicated register set when said program branch is taken.  
     
     
       16. The computer program of  claim 15 , wherein said second loadable dedicated register set can be loaded with branch target instructions in advance of execution of said first and/or second instructions. 
     
     
       17. The computer program of  claim 15 , wherein said program branch of said second instruction is configured with a priority value ranging from 1 to n, where n>2, said priority value indicating a relative frequency of said program branch being taken. 
     
     
       18. The computer program of  claim 17 , where said priority value is used by the computing machine to determine whether instructions should be pre-loaded into said second loadable dedicated register set for said program branch in advance of said program branch being executed. 
     
     
       19. The computer program of  claim 18 , wherein said priority value is provided by said first register selection field, such that said priority value identifies a corresponding register in the first loadable dedicated register set. 
     
     
       20. The computer program of  claim 15 , wherein said first instruction includes a first prediction field indicating whether said branch target instruction is likely to be executed by a program branch, and said second instruction includes a second prediction field indicating whether said program branch is likely to be taken.