Method and apparatus for switching clocks presented to synchronous SRAMs

Abstract

A method and apparatus for switching clocks comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate (i) a first signal in response to a select signal and a first clock signal, (ii) a second signal in response to said first signal and a second clock signal, (iii) a third signal in response to said select signal and said second clock signal, and (iv) a fourth signal in response to said third signal and said first clock signal. The second circuit may be configured to generate a first enable signal and a second enable signal in response to (i) said first signal, (ii) said second signal, (iii) said third signal, and (iv) said fourth signal. The third circuit may be configured to select (i) one or more first input signals, (ii) one or more second input signals, or (iii) a predetermined logic level as one or more output signals in response to said first enable signal and said second enable signal.

What is claimed is:  
     
       1. An apparatus comprising: 
       a first circuit configured to generate (i) a first signal in response to a select signal and a first clock signal, (ii) a second signal in response to said first signal and a second clock signal, (iii) a third signal in response to said select signal and said second clock signal, and (iv) a fourth signal in response to said third signal and said first clock signal;  
       a second circuit configured to generate a first enable signal and a second enable signal in response to (i) said first signal, (ii) said second signal, (iii) said third signal, and (iv) said fourth signal; and  
       a third circuit configured to select (i) one or more first input signals, (ii) one or more second input signals, or (iii) a predetermined logic level as one or more output signals in response to said first enable signal and said second enable signal, wherein said first enable signal and said second enable signal have transitions only when said one or more output signals are at said predetermined logic level.  
     
     
       2. The apparatus according to  claim 1 , wherein said second circuit comprises a state machine. 
     
     
       3. The apparatus according to  claim 2 , wherein said state machine comprises a 4-state asynchronous state machine. 
     
     
       4. The apparatus according to  claim 1 , wherein one of said one or more output signals is a clock signal presented to a clock input of one or more memories. 
     
     
       5. The apparatus according to  claim 4 , wherein said one or more memories comprise one or more synchronous SRAMs. 
     
     
       6. The apparatus according to  claim 4 , wherein said predetermined logic level comprises an inactive state of said clock input. 
     
     
       7. The apparatus according to  claim 1 , wherein said third circuit selects said one or more first input signals or said one or more second input signals only after a selection of said predetermined logic level. 
     
     
       8. The apparatus according to  claim 1 , wherein said first circuit comprises: 
       a first synchronizing circuit and a first pulse generation circuit configured to generate said first signals; and  
       a second synchronizing circuit and a second pulse generation circuit configured to generate said third signal.  
     
     
       9. The apparatus according to  claim 8 , further comprising: 
       a third synchronizing circuit configured to generate said second signal in response to said first signal and said second clock signal; and  
       a fourth synchronizing circuit configured to generate said fourth signal in response to said third signal and said first clock signal.  
     
     
       10. The apparatus according to  claim 1 , wherein: 
       said first circuit comprises (i) a first synchronizing circuit, (ii) a first one-clock-pulse generator circuit, (iii) a first sync pulse transfer circuit, (iv) a second synchronizing circuit, (v) a second one-clock-pulse generator circuit, (vi) a second sync pulse transfer circuit; and  
       said second circuit comprises (i) a first AND gate, (ii) a second AND gate, (iii) a third AND gate, (iv) a fourth AND gate, (v) a first S-R latch, (vi) a second S-R latch, (vii) a third S-R latch, and (viii) a fourth S-R latch; and  
       said third circuit comprises (i) a first OR gate, (ii) a second OR gate, and (iii) an AND gate.  
     
     
       11. An apparatus comprising: 
       means for generating (i) a first signal in response to a select signal and a first clock signal, (ii) a second signal in response to said first signal and a second clock signal, (iii) a third signal in response to said select signal and said second clock signal, and (iv) a fourth signal in response to said third signal and said first clock signal;  
       means for generating a first enable signal and a second enable signal in response to (i) said first signal, (ii) said second signal, (iii) said third signal, and (iv) said fourth signal; and  
       means for selecting (i) one or more first input signals, (ii) one or more second input signals, or (iii) a predetermined logic level as one or more output signals in response to said first enable signal and said second enable signal, wherein said first enable signal and said second enable signal have transitions only when said one or more output signals are at said predetermined logic level.  
     
     
       12. A method for switching clocks presented to a memory comprising the steps of: 
       (A) generating (i) a first signal in response to a select signal and a first clock signal, (ii) a second signal in response to said first signal and a second clock signal, (iii) a third signal in response to said select signal and said second clock signal, and (iv) a fourth signal in response to said third signal and said first clock signal;  
       (B) generating a first enable signal and a second enable signal in response to (i) said first signal, (ii) said second signal, (iii) said third signal, and (iv) said fourth signal; and  
       (C) selecting (i) one or more first input signals, (ii) one or more second input signals, or (iii) a predetermined logic level as one or more output signals in response to said first enable signal and said second enable signal, wherein said first enable signal and said second enable signal have transitions only when said one or more output signals are at said predetermined logic level.  
     
     
       13. The method according to  claim 12 , wherein said memory comprises a synchronous SRAM. 
     
     
       14. The method according to  claim 12 , wherein the step (A) further comprises the sub-steps of: 
       (A-1) generating a first synchronized control signal by sampling a digital complement of said select signal with said first clock signal;  
       (A-2) generating said first signal as a pulse having a pulse width equal to one half of the period of said first clock signal in response to a positive transition of said first synchronized control signal;  
       (A-3) generating said second signal as a pulse having a pulse width equal to one half of the period of said second clock in response to a positive transition of, said first signal;  
       (A-4) generating a second synchronized control signal by sampling said select signal with said second clock signal;  
       (A-5) generating said third signal as a pulse having a pulse width equal to one half of the period of said second clock signal in response to a positive transition of said second synchronized control signal; and  
       (A-6) generating said fourth signal as a pulse having a pulse width equal to one half of the period of said first clock in response to a positive transition of said third signal.  
     
     
       15. The method according to  claim 12 , wherein the step (B) further comprises the sub-steps of: 
       (B-1) checking a state of a second circuit;  
       (B-2) if said state of said second circuit is a first state, (i) changing said state of said second circuit to a second state and (ii) setting said first enable signal and said second enable signal to a first logic state upon a positive transition of said first signal;  
       (B-3) if said state of said second circuit is said second state, (i) changing said second circuit to a third state, (ii) setting said first enable signal to said first logic state, and (iii) setting said second enable signal to a second logic state upon a positive transition of said second signal;  
       (B-4) if said state of said second circuit is said third state, (i) changing the state of said second circuit to a fourth state and (ii) setting said first enable signal and said second enable signal to said first logic state upon a positive transition of said third signal; and  
       (B-5) if said state of said second circuit is in said fourth state, (i) changing said state of said second circuit to said first state, (ii) setting said first enable signal to said second logic state, and (iii) setting said second enable signal to said first logic state upon a positive transition of said fourth signal.  
     
     
       16. The method according to  claim 12 , wherein the step (C) further comprises the sub-steps of: 
       (C-1) generating a logical combination of said first enable signal and said one or more first input signals;  
       (C-2) generating a logical combination of said second enable signal and said one or more second input signals; and  
       (C-3) generating a logical combination of the result of sub-step (C-1) and the result of sub-step (C-2).  
     
     
       17. The method according to  claim 12 , wherein: 
       step (A) further comprises the sub-steps of (A-1) generating a first synchronized control signal by sampling a digital complement of said select signal with said first clock signal, (A-2) generating said first signal as a pulse having a pulse width equal to one half of the period of said first clock signal in response to a positive transition of said first synchronized control signal, (A-3) generating said second signal as a pulse having a pulse width equal to one half of the period of said second clock in response to a positive transition of said first signal, (A-4) generating a second synchronized control signal by sampling said select signal with said second clock signal, (A-5) generating said third signal as a pulse having a pulse width equal to one half of the period of said second clock signal in response to a positive transition of said second synchronized control signal, and (A-6) generating said fourth signal as a pulse having a pulse width equal to one half of the period of said first clock in response to a positive transition of said third signal;  
       step (B) further comprises the sub-steps of (B-1) checking a state of said second circuit, (B-2) if a second state of said second circuit is a first state, (i) changing said state of said second circuit to a second state and (ii) setting said first enable signal and said second enable signal to a first logic state upon a positive transition of said first signal, (B-3) if said state of said second circuit is said second state, (i) changing said second circuit to a third state, (ii) setting said first enable signal to said first logic state, and (iii) setting said second enable signal to a second logic state upon a positive transition of said second signal, (B-4) if said state of said second circuit is said third state, (i) changing the state of said second circuit to a fourth state and (ii) setting said first enable signal and said second enable signal to said first logic state upon a positive transition of said third signal, and (B-5) if said state of said second circuit is in said fourth state, (i) changing said state of said second circuit to said first state, (ii) setting said first enable signal to said second logic state, and (iii) setting said second enable signal to said first logic state upon a positive transition of said fourth signal; and  
       step (C) further comprises the sub-steps of (C-1) generating a logical combination of said first enable signal and said one or more first input signals, (C-2) generating a logical combination of said second enable signal and said one or more second input signals and (C-3) generating a logical combination of the result of sub-step (C-1) and the result of sub-step (C-2).