Oversampling clock recovery circuit

Abstract

Differential clocks CLKa, CLKb are supplied, and controlled in phase by a phase control circuit. Based on differential clocks CLKa, CLKb that have been controlled in phase by the phase control circuit, a delay-locked loop (DLL) generates 16-phase clocks CLK 1 through CLK 16 , and supplies generated 16-phase clocks CLK 1 through CLK 16 to phase comparators PD 2. A control voltage V 2 generated by a phase control signal based on phase difference information (UP/DOWN signal) outputted from phase comparators PD 2 is supplied via a feedback loop to the phase control circuit, which uses control voltage V 2 for the control of the phase of differential clocks CLKa, CLKb.

What is claimed is:  
     
       1. An oversampling clock recovery circuit having a plurality of phase comparators sampling for phase comparison an inputted data signal with a number of generated clocks which are out of phase with each other, said plurality of phase comparators providing phase difference information to control the phase of the generated clocks, said oversampling clock recovery circuit comprising: 
       a phase control circuit supplied with fewer clocks than said number of generated clocks for controlling the phase of the generated clocks; and  
       a delay-locked loop for generating said number of generated clocks based on said fewer clocks controlled for phase by said phase control circuit, and supplying the generated number of clocks to said phase comparators,  
       wherein a phase control signal based on the phase difference information output from the phase comparators is supplied via a feedback loop to said phase control circuit.  
     
     
       2. The oversampling clock recovery circuit according to  claim 1 , wherein said fewer clocks comprise one or two clocks. 
     
     
       3. The oversampling clock recovery circuit according to  claim 1 , wherein said fewer clocks comprise one clock. 
     
     
       4. An oversampling clock recovery circuit, comprising: 
       a delay-locked loop generating a plurality of clock signals;  
       a plurality of phase detectors corresponding in number to said plurality of clock signals, each said phase detector receiving a predetermined one of said plurality of clock signals to compare with an input data signal; and  
       a phase control circuit receiving, as a first input, at least one signal from said plurality of phase detectors via a feedback loop comprising said delay-locked loop and said plurality of phase detectors and, as a second input, at least one clock reference signal.  
     
     
       5. The clock recovery circuit of  claim 4 , further comprising: 
       a circuit generating said at least one clock reference signal.  
     
     
       6. The clock recovery circuit of  claim 4 , wherein said at least one signal from said plurality of phase detectors comprises a single signal. 
     
     
       7. The clock recovery circuit of  claim 4 , wherein said clock reference signal comprises a single signal.