Monolithic integrated circuit implemented in a digital display unit for generating digital data elements from an analog display signal received at high frequencies

Abstract

A monolithic integrated circuit for use in a digital display unit. The circuit may include an analog-to-digital converter (ADC), a scaler and a clock recovery circuit. The present invention enables the integration of at least these components into a single monolithic integrated circuit while maintaining reasonable display quality. Specifically, the monolithic integrated circuit is designed for substantial immunity from noise, which may otherwise result from integration.

What is claimed is:  
     
       1. A monolithic integrated circuit for use in a digital display unit, wherein said monolithic integrated circuit receives an analog display signal encoded with a plurality of images, said analog display signal comprising display data signal and associated synchronization signals, said monolithic integrated circuit generating a plurality of pixel data elements for display on a digital display screen contained in said digital display unit, said monolithic integrated circuit comprising: 
       a clock generator circuit for generating a sampling clock synchronized with said synchronization signals;  
       an analog to digital converter (ADC) for receiving said display data signal and sampling said display data signal according to said sampling clock to generate a plurality of sampled data elements representing an image encoded in said display data signal: and  
       an scaler for scaling said image by processing said plurality of sampled data elements to generate a plurality of pixel data elements,  
       wherein said plurality of pixel data elements are used to display said scaled image on said digital display screen, and  
       wherein said scaler is implemented to use no more memory than two lines of said scaled image, wherein said lesser memory enables said scaler to be integrated into said monolithic integrated circuit.  
     
     
       2. A display unit for displaying a plurality of images encoded in an analog display signal, said analog display signal comprising a display data signal and associated synchronization signals, said display unit comprising: 
       a display screen;  
       a panel interface coupled to said display screen; and  
       a monolithic integrated circuit generating a plurality of pixel data elements for display on said display screen, said monolithic integrated circuit comprising:  
       a clock generator circuit for generating a sampling clock synchronized with said synchronization signals;  
       an analog to digital converter (ADC) for receiving said display data signal and sampling said display data signal according to said sampling clock to generate a plurality of sampled data elements representing an image encoded in said display data signal; and  
       a scaler for scaling said image by processing said plurality of sampled data elements to generate a plurality of pixel data elements,  
       wherein said panel interface uses said plurality of pixel data elements to display said scaled image on said digital display screen, and  
       wherein said scaler is implemented to use no more memory than two lines of said image, and  
       wherein said lesser memory enables said scaler to be integrated into said monolithic integrated circuit.  
     
     
       3. A self-calibrating monolithic integrated display circuit, comprising: 
       a plurality of analog to digital converters (ADCs), each ADC having a color balance register, and each ADC converting in accordance with its respective color balance register;  
       a single digital to analog converter (DAC), having a DAC register connected to said DAC, said DAC generating an output signal in accordance with the contents of the DAC register; and  
       a multiplexor, having a plurality of input pairs, each pair comprising a DAC input from said DAC and a display input from an external display signal, said multiplexor capable of simultaneously directing only the external display signal to said plurality of ADCs, and said multiplexor also capable of multiplexing only the DAC input to said plurality of ADCs.  
     
     
       4. The circuit according to  claim 3 , further comprising a control processor connected to said multiplexor, the DAC register, and each of the ADC color balance registers, said control processor calibrating the first ADC by directing said multiplexor to direct the DAC input to the first ADC, setting the DAC register to a base value, and setting the color balance register of the first ADC according to both the base value and a resulting output voltage of the first DAC. 
     
     
       5. The circuit according to  claim 4 , wherein during the calibrating of the first ADC, said control processor sets the color balance register of the first ADC such that the output voltage of the first ADC is essentially equal to the base value. 
     
     
       6. The circuit according to  claim 4 , wherein said control processor performs the calibrating on each ADC and its associated color balance register. 
     
     
       7. The circuit according to  claim 4 , further comprising a timing recovery component that recovers the timing of the external source signal and supplies the timing to a clock component that drives the circuit.