System and method for efficient layout of functionally extraneous cells

Abstract

A method for defining electrical components enables a layout tool to include functionally extraneous cells in an integrated circuit design without significant adverse impact to the operation of the logically functional cells. The method defines the description of a first functionally extraneous cell for a layout tool so an initial layout of the die produced by the layout tool does not functionally couple the first functionally extraneous cell to a second functionally extraneous cell. The description of the functionally extraneous cell is altered so that the layout tool produces a second layout of the die that functionally couples the first and second functionally extraneous cells without altering the position of the second functionally extraneous cell with respect to a logically functional cell. The description of the functionally extraneous cell complies with the description constraints for cells. However, by describing the functionally extraneous cell so that it is first lacks a functional coupling to another extraneously functional cell and then changing the description to functionally couple the two cells, the position of the second functional cell with respect to a functional cell remains unchanged. In this manner, the advantages of the layout tool may be used to most efficiently locate the cells of the logically functional cells and then couple test circuitry or other functionally extraneous circuits without adversely impacting the operation of the functional logic in a significant way.

What is claimed is:  
     
       1. A method for including functionally extraneous cells on an integrated circuit die without significant adverse impact to logically functional cells of the integrated circuit comprising: 
       defining the description of a first functionally extraneous cell for a layout tool so an initial area map of the die produced by the layout tool does not functionally couple the first functionally extraneous cell to a second functionally extraneous cell and so an output of the first functionally extraneous cell is defined at an intermediate hierarchical level as being connected to signal ground; and  
       altering the description of the first functionally extraneous cell so that the output of the first functionally extraneous cell is defined at the intermediate hierarchical level as being disconnected from signal ground and so that the layout tool produces a second area map of the die that functionally couples said first functionally extraneous cell to said second functionally extraneous cell whereby the position of the second functionally extraneous cell with respect to a logically functional cell does not change between the first and second layouts.  
     
     
       2. The method of  claim 1 , wherein: 
       said functionally extraneous cell implements a signal buffer; and  
       said logically functional cell implements at least a portion of timing sensitive circuitry.  
     
     
       3. The method of  claim 1 , wherein: 
       said functionally extraneous cell is included in an intermediate hierarchical level; and  
       said altered description is a description for said intermediate hierarchical level.  
     
     
       4. The method of  claim 1 , wherein the first logically functional cell comprises a high speed state machine. 
     
     
       5. The method of  claim 1 , wherein the first functionally extraneous cell comprises a buffer. 
     
     
       6. The method of  claim 1 , wherein the second logically functional cell comprises an output pad. 
     
     
       7. The method of  claim 1 , wherein the second functionally extraneous cell comprises a test multiplexer. 
     
     
       8. The method of  claim 1 , wherein the connection between the first and second functionally extraneous cells is substantially longer than the connection between the first functionally extraneous cell and an associated logically functional cell. 
     
     
       9. The method of  claim 1 , wherein the connection between the first and second functionally extraneous cells is substantially longer than the connection between the second functionally extraneous cell and the logically functional cell. 
     
     
       10. The method of  claim 1 , wherein the first functionally extraneous cell is placed as closely as possible to an associated logically functional cell as governed by a program that generates the first layout.