Voltage level shifter and phase splitter

Abstract

A high speed voltage level shifter and phase splitter circuit is provided. The voltage level shifter and phase splitter circuit includes an input signal and a first input inverter stage that receives the input signal and provides an inverted delayed out of phase signal to the input signal. A buffer stage receives the input signal and provides a buffered delayed in phase signal to the input signal. A first constant current source is coupled between the first input inverter stage and the buffer stage. A first output inverter stage is coupled to the first constant current source and provides a voltage level shifted and out of phase signal to the input signal. A second constant current source is coupled between the first input inverter stage and the buffer stage having an opposite polarity as the first constant current source. A second output inverter stage is coupled to the second constant current source and providing a voltage level shifted and in phase signal to the input signal.

What is claimed is:  
     
       1. A voltage level shifter and phase splitter circuit comprising: 
       an input signal;  
       a first input inverter stage receiving said input signal and providing an inverted delayed out of phase signal to said input signal;  
       a buffer stage receiving said input signal and providing a buffered delayed in phase signal to said input signal;  
       a first constant current source coupled between said first input inverter stage and said buffer stage;  
       a first output inverter stage coupled to said first constant current source and providing a voltage level shifted and out of phase signal to said input signal;  
       a second constant current source coupled between said first input inverter stage and said buffer stage with an opposite polarity as said first constant current source; and  
       a second output inverter stage coupled to said second constant current source and providing a voltage level shifted and in phase signal to said input signal.  
     
     
       2. A voltage level shifter and phase splitter circuit as recited in  claim 1  wherein said buffer stage receiving said input signal and providing said buffered delayed in phase signal to said input signal includes a pair of inverter stages. 
     
     
       3. A voltage level shifter and phase splitter circuit as recited in  claim 1  wherein each of said first constant current source and said second constant current source includes a pair of P-channel field effect transistors (PFETs) having a source coupled to a voltage supply VDDQ and each of said pair of PFETs being self-biased to function as a resistor. 
     
     
       4. A voltage level shifter and phase splitter circuit as recited in  claim 3  wherein each of said first constant current source and said second constant current source includes a pair of N-channel field effect transistors (NFETs) connected in series with said pair of PFETs and said pair of NFETs having a source connection to a drain of a third N-channel field effect transistor (NFET) and having a respective gate connection to a respective output of said first input inverter stage and said buffer stage; said third NFET having a source connected to ground and being constantly on. 
     
     
       5. A voltage level shifter and phase splitter circuit as recited in  claim 4  wherein each of said first constant current source and said second constant current source includes a respective drain connection of a respective one of said pair of series connected PFETs and NFETs respectively connected to said first output inverter stage and said second output inverter stage. 
     
     
       6. A voltage level shifter and phase splitter circuit as recited in  claim 5  wherein each of said first output inverter stage and said second output inverter stage include a series connected P-channel field effect transistor and N-channel field effect transistor connected between said voltage supply VDDQ and ground and having a gate connection to said respective drain connection of one of said first constant current source and said second constant current source. 
     
     
       7. A voltage level shifter and phase splitter circuit as recited in  claim 1  wherein said first input inverter stage receiving said input signal and providing said inverted delayed out of phase signal to said input signal and said buffer stage receiving said input signal and providing a buffered delayed in phase signal to said input signal are arranged to provide approximately equal delay. 
     
     
       8. A voltage level shifter and phase splitter circuit as recited in  claim 1  wherein said voltage level shifted and out of phase signal to said input signal provided by said first output inverter stage and said voltage level shifted and in phase signal to said input signal provided said second output inverter stage are substantially balanced outputs. 
     
     
       9. A voltage level shifter and phase splitter circuit comprising: 
       an input signal;  
       a first input inverter stage receiving said input signal and providing an inverted delayed out of phase signal to said input signal;  
       a buffer stage receiving said input signal and providing a buffered delayed in phase signal to said input signal; said inverted delayed out of phase signal to said input signal and said buffered delayed in phase signal. to said input signal having approximately equal delay;  
       a first constant current source coupled between said first input inverter stage and said buffer stage;  
       a first output inverter stage coupled to said first constant current source and providing a voltage level shifted and out of phase signal to said input signal;  
       a second constant current source coupled between said first input inverter stage and said buffer stage with an opposite polarity as said first constant current source; and  
       a second output inverter stage coupled to said second constant current source and providing a voltage level shifted and in phase signal to said input signal; said voltage level shifted and out of phase signal to said input signal provided by said first output inverter stage and said voltage level shifted and in phase signal to said input signal provided said second output inverter stage being substantially balanced outputs.  
     
     
       10. A voltage level shifter and phase splitter circuit as recited in  claim 9  wherein each of said first constant current source and said second constant current source includes a pair of P-channel field effect transistors (PFETs) having a source coupled to a voltage supply VDDQ and each of said pair of PFETs being self-biased to function as a resistor. 
     
     
       11. A voltage level shifter and phase splitter circuit as recited in  claim 10  wherein each of said first constant current source and said second constant current source includes a pair of N-channel field effect transistors (NFETs) connected in series with said pair of PFETs and said pair of NFETs having a source connection to a drain of a third N-channel field effect transistor (NFET) and having a respective gate connection to a respective output of said first input inverter stage and said buffer stage; said third NFET having a source connected to ground and being constantly on. 
     
     
       12. A voltage level shifter and phase splitter circuit as recited in  claim 11  wherein each of said first constant current source and said second constant current source includes a respective drain connection of a respective one of said pair of series connected PFETs and NFETs respectively connected to said first output inverter stage and said second output inverter stage. 
     
     
       13. A voltage level shifter and phase splitter circuit as recited in  claim 12  wherein each of said first output inverter stage and said second output inverter stage include a series connected P-channel field effect transistor and N-channel field effect transistor connected between said voltage supply VDDQ and ground and having a gate connection to said respective drain connection of one of said first constant current source and said second constant current source.