Termination structure for high speed, high pin density chips

Abstract

An apparatus including first and second devices, at least one connection between an input of the second device and an output of the first device, and at least one resistor in series between the connection and the input of the second device. The series resistor, acting as a type of end termination, positively alters the waveforms of the signals input to the second device. In particular, glitches and ringing after the input pin package or at the input of the second device (at the gate for a CMOS transistor) are reduced. Overshoots and undershoots are also reduced. As a result, the input signals are usable and the interface between the first and second devices operates correctly. Further, the setup procedure of the valid logic level of the input signal can be accomplished much more quickly and is much more stable. The series resistor also consumes very little extra power.

What is claimed is:  
     
       1. An apparatus comprising: 
       a first device and  
       a second device,  
       said first and second devices each being a packaged microchip;  
       at least one connection between at least one input of said second device and at least one output of said first device: and  
       a termination structure comprising at least one external resistor, between said connection and said at least one input of said second device, said termination structure being in series with said connection and with said at least one input of said second device.  
     
     
       2. The apparatus of  claim 1 , said first and second device each being one of a high pin density package device or a MOS VLSI chip. 
     
     
       3. The apparatus of  claim 1 , said connection being one of a PCB trace, wire, cable, connector, bridge, or via. 
     
     
       4. The apparatus of  claim 1 , wherein said at least one resistor acts as an end termination for a unidirectional interface from said first device to said second device. 
     
     
       5. The apparatus of  claim 1 , further comprising at least one termination arrangement between said first device and said connection. 
     
     
       6. The apparatus of  claim 5 , wherein said at least one resistor acts as a source termination for a unidirectional interface from said second device to said first device. 
     
     
       7. The apparatus of  claim 5 , wherein a bi-directional interface is established between said first device and said second device. 
     
     
       8. The apparatus of  claim 1 , wherein said at least one resistor is part of the package of said second device. 
     
     
       9. The apparatus of  claim 1 , wherein a value of the at least one resistor depends on the signal propagated by said at least one connection. 
     
     
       10. The apparatus of  claim 5 , said first and second devices each being one of an asynchronous transfer mode (ATM) device or a physical layer (PHY) device. 
     
     
       11. The apparatus of  claim 9 , wherein a value of the at least one resistor depends on the overshoot and/or undershoot requirement of the second device. 
     
     
       12. The apparatus of  claim 9 , wherein the value of the at least one resistor depends on the rise time and/or fall time requirement of the signal. 
     
     
       13. The apparatus of  claim 9 , wherein the value of the at least one resistor is determined using transistor-level simulation. 
     
     
       14. The apparatus of  claim 1 , wherein the at least one resistor includes at least one discrete component. 
     
     
       15. A method for providing an interface between a first and second packaged microchip, comprising: 
       connecting an input of sad second microchip and an output pin of said first microchip with a signal transmission medium;  
       inserting a termination structure comprising an external resistor between said signal transmission medium and said input of said second microchip such that said termination structure is in series with said signal transmission medium and with said input of said second microchip.  
     
     
       16. The method of  claim 15 , said first and second packaged microchips each being one of a high pin density chip or a MOS VLSI chip. 
     
     
       17. The method of  claim 15 , said connection being one of a PCB trace, wire, cable, connector, bridge, or via. 
     
     
       18. The method of  claim 15 , wherein said at least one resistor acts as an end termination for a unidirectional interface from said first packaged microchip to said second packaged microchip. 
     
     
       19. The method of  claim 15 , further comprising: 
       inserting at least one termination arrangement between said first packaged microchip and said signal transmission medium.  
     
     
       20. The method of  claim 19 , wherein said at least one resistor acts as a source termination for a unidirectional interface from said second packaged microchip to said first packaged microchip. 
     
     
       21. The method of  claim 19 , wherein a bi-directional interface is established between said first packaged microchip and said second packaged microchip. 
     
     
       22. The method of  claim 15 , wherein a value of the at least one resistor depends on the overshoot and/or undershoot requirement of the second packaged microchip. 
     
     
       23. The method of  claim 15 , wherein a value of the at least one resistor depends on the rise time and/or fall time requirement of the signal propagated by said signal transmission medium. 
     
     
       24. The apparatus of  claim 15 , wherein the value of the at least one resistor is determined using transistor-level simulation. 
     
     
       25. The apparatus of  claim 15 , wherein the at least one resistor includes at least one discrete component.