Class AB single-range advanced operational amplifier

Abstract

A class AB single-stage operational amplifier having input decoupler stages for voltage signals, a voltage repeater stage, biasing transistors and bias current generators for the input decoupler stages, and capacitors placed between the input decoupler stages and the voltage repeater stage so as to increase the phase margin.

What is claimed is:  
     
       1. A class AB single-stage operational amplifier comprising: 
       first and second input decoupler stages having inputs for the operational amplifier for voltage signals, a voltage repeater stage, biasing means, and means for the generation of bias current of said input decoupler stages, and capacitive means placed between said input decoupler stages and said voltage repeater so as to eliminate a low frequency pole and increase the phase margin.  
     
     
       2. The operational amplifier of  claim 1 , wherein said capacitive means are placed between gate terminals of transistors constituting said voltage repeater and gate terminals of transistors constituting said input decoupler stages. 
     
     
       3. The operational amplifier of  claim 2 , wherein said capacitive means are of a much greater capacity in comparison to the capacitive load of said input decoupler stages. 
     
     
       4. The operational amplifier of  claim 3 , wherein the capacitive means is configured to generate an output having a low frequency pole that coincides with a low frequency zero. 
     
     
       5. An operational amplifier, comprising: 
       a first input decoupler stage coupled between a first voltage source and a second voltage source and having inputs comprising inputs to the operational amplifier;  
       a second input decoupler stage coupled between the first voltage source and the second voltage source;  
       a voltage repeater stage coupled between the first input decoupler stage and the second input decoupler stage;  
       a first compensation capacitor coupled in parallel between the voltage repeater stage and the first input decoupler stage; and  
       a second compensation capacitor coupled in parallel between the voltage repeator stage and the second input decoupler stage.  
     
     
       6. The operational amplifier of  claim 5 , further comprising first, second, third, and fourth loads, and wherein the voltage repeater stage comprises first, second, third, and fourth MOS transistors, the first and fourth MOS transistors coupled in series between the first and fourth loads, and the second and third MOS transistors coupled in series between the second and third loads, and further wherein the first compensation capacitor has a first end coupled to a gate terminal of the first MOS transistor and a second end coupled to a gate terminal of the third MOS transistor, and the second compensation capacitor has a first end coupled to the gate terminal of the second MOS transistor and a second end coupled to the fourth MOS transistors. 
     
     
       7. The operational amplifier of  claim 6 , further comprising fifth, sixth, seventh, and eighth MOS transistors, wherein the first input decoupler stage comprises the fifth and seventh MOS transistors coupled in series between the first and third loads, and the second input decoupler stage comprises the sixth and eighth MOS transistors coupled between the second and fourth loads, and wherein the first compensation capacitor is further coupled to gate terminals of the fifth and seventh MOS transistors, and the second compensation capacitor is further coupled to gate terminals of the sixth and eighth MOS transistors. 
     
     
       8. The operational amplifier of  claim 5  wherein the first and second compensation capacitors are configured so that the frequency of a low frequency pole and the frequency of a low frequency zero of the circuit output coincide and a phase margin is increased. 
     
     
       9. The operational amplifier of  claim 5 , wherein the capacitance of each compensation capacitor is greater than the capacitance of each corresponding input decoupling stage. 
     
     
       10. The operational amplifier of  claim 5 , wherein the capacitance of each compensation capacitor is about three times greater than the capacitance of each corresponding input decoupler stage. 
     
     
       11. The operational amplifier of  claim 5 , configured to have a small signal model comprising: 
       a voltage input;  
       a gate-source capacitance coupled between the voltage input and a first voltage node;  
       a current source coupled between a ground reference and the first voltage node;  
       a resistance coupled between the first voltage node and a voltage output;  
       a parallel resistance-capacitance circle coupled between the voltage output and the ground reference; and  
       a compensation capacitor coupled to the voltage input and the voltage output.  
     
     
       12. A fully differential operational amplifier, comprising: 
       an inverting input circuit and a non-inverting input circuit coupled between a voltage source and a voltage reference;  
       a voltage repeater stage coupled between the inverting input circuit and the non-inverting input circuit;  
       an inverting and non-inverting output circuit coupled to the voltage repeater stage;  
       the inverting input circuit comprising a first PMOS transistor having a gate terminal coupled to an inverting input terminal and a first NMOS transdiode transistor coupled in series to the first PMOS transistor;  
       the non-inverting input circuit comprising a second PMOS transistor having a gate terminal coupled to a non-inverting input terminal and a second NMOS transdiode transistor coupled in series to the second PMOS transistor;  
       a first compensation capacitor coupled between gate terminals of the first PMOS transistor and first NMOS transdiode transistor; and  
       a second compensation capacitor coupled between gate terminals of the second PMOS transistor and the second NMOS transdiode transistor.  
     
     
       13. The amplifier of  claim 12 , wherein the voltage repeater stage comprises first, second, third, and fourth MOS transistors, the first and fourth MOS transistors coupled in series between a first load and fourth load, and the second and third MOS transistors coupled in series between the second and third loads, and wherein the first compensation capacitor is coupled to gate terminals of the first and third MOS transistors, and the second compensation capacitor is coupled to gate terminals of the second and fourth MOS transistors. 
     
     
       14. The amplifier of  claim 13 , configured to have a small signal model comprising: 
       a voltage input;  
       a gate-source capacitance coupled between the voltage input and the first voltage node;  
       a current source coupled between a ground reference and the first node;  
       a resistance coupled between the first voltage node and a voltage output;  
       a parallel resistance-capacitance circuit coupled between the voltage output and the ground reference; and  
       a compensation capacitor coupled to the voltage input and the voltage output.  
     
     
       15. A method for increasing the phase margin of an operational amplifier having a first input decoupler stage coupled between a first voltage source and a second voltage source; a second input decoupler stage coupled between the first voltage source and the second voltage source; a voltage repeater stage coupled between the first input decoupler stage and the second input decoupler stage, the method comprising: 
       coupling a first compensation capacitor in parallel between the voltage repeater stage and the first input decoupler stage; and  
       coupling a second compensation capacitor in parallel between the voltage repeater stage and the second input decoupler stage.  
     
     
       16. The method of  claim 15 , wherein the operational amplifier further includes first, second, third, and fourth loads, and a voltage repeater stage includes first, second, third, and fourth MOS transistors, with the first and fourth MOS transistors coupled in series between the first and fourth loads, and the second and third MOS transistors coupled in series between the second and third loads, and wherein the method comprises: 
       coupling the first compensation capacitor to gate terminals of the first and third MOS transistors; and  
       coupling the second compensation capacitor to gate terminals of the second and fourth MOS transistors.  
     
     
       17. The method of  claim 15 , wherein the operational amplifier includes fifth, sixth, seventh, and eighth input stage MOS transistors, the first input decoupling stage having the fifth and seventh MOS transistors coupled in series between the first and third loads, the second input decoupling stage including the sixth and eighth MOS transistors coupled in series between the second and fourth loads, and wherein the method comprises: 
       coupling the first compensation capacitor to gate terminals of the fifth and seventh MOS transistors; and  
       coupling the second compensation capacitor to gate terminals of the sixth and eighth MOS transistors.  
     
     
       18. The method of  claim 15 , comprising: 
       configuring the first and second compensation capacitors so that the frequency of a low frequency pole and the frequency of a low frequency zero of the circuit coincide and the phase margin is increased.  
     
     
       19. The method of  claim 14 , comprising: 
       configuring the capacitance of the first and second compensation capacitors to be greater than a capacitance of each corresponding input decoupler stage.  
     
     
       20. A class AB single-stage operational amplifier, comprising: 
       input decoupler stages for voltage signals that are formed by MOS transistors, a voltage repeater stage formed by MOS transistors, a common gate terminal of at least one MOS transistor of the input decoupler stages and of at least one MOS transistor of the voltage repeater stage forming the input terminals of the class AB single-stage operational amplifier, biasing means, and means for the generation of bias current of the input decoupler stages, and further comprising capacitive means connected to the input terminal of the class AB single-stage operational amplifier and another common gate terminal of another MOS transistor of the input decoupler stages and of another MOS transistor of the voltage repeater stage so as to generate an output having a low frequency pole that coincides with a low frequency zero.