Semiconductor wafer with scribe lines having inspection pads formed thereon

Abstract

A plurality of IC chips each having an internal circuit are mounted on a wafer substrate. A plurality of scribe lines are formed on the wafer substrate for separating the IC chips from one another. A plurality of inspection pads are formed on the scribe lines. Each of the inspection pads is connected to the associated internal circuit via a conduction path for inspecting an operation of the associated IC chip.

What is claimed is:  
     
       1. A semiconductor wafer, comprising: 
       a wafer substrate;  
       a plurality of IC chips mounted on the wafer substrate, each of the IC chips having an internal circuit;  
       a plurality of scribe lines formed on the wafer substrate for separating the IC chips from one another; and  
       a plurality of inspection pads formed on the scribe lines, each of the inspection pads being connected to the associated internal circuit via a conduction path for inspecting an operation of the associated IC chip,  
       wherein the conduction path is formed in the wafer substrate.  
     
     
       2. The semiconductor wafer as set forth in  claim 1 , further comprising a plurality of protection devices formed on the scribe lines, each of the protection devices being connected to the associated inspection pad and the associated internal circuit for preventing an overcurrent from being supplied to the internal circuit. 
     
     
       3. The semiconductor wafer as set forth in  claim 1 , wherein the conduction path is made of polysilicon. 
     
     
       4. A semiconductor wafer as set forth in  claim 2 , wherein said protection devices formed on said scribe lines comprise one or more diffusions which extend within said semiconductor wafer. 
     
     
       5. A semiconductor wafer as set forth in  claim 4 , wherein said protection devices are in the form of diodes comprising an N diffusion layer and a P diffusion layer. 
     
     
       6. A semiconductor wafer as set forth in  claim 2  wherein said inspection pads are connected to an emitter of a transistor of said internal circuit of said plurality of IC chips. 
     
     
       7. A semiconductor wafer as set forth in  claim 6  wherein said protection devices are diodes, and wherein said inspection pads are also connected to cathode terminals of said diodes. 
     
     
       8. A semiconductor wafer as set forth in  claim 3  wherein said conduction path which connects said internal circuit to inspection pads on said wafer substrate includes a sacrificial portion that is located within a boundary of said IC chip. 
     
     
       9. A semiconductor wafer as set forth in  claim 1 , wherein the plurality of inspection pads are formed in the scribe lines situated between the IC chips. 
     
     
       10. A semiconductor wafer as set forth in  claim 2 , wherein the plurality of protection devices are buried in the wafer substrate under the scribe lines.