Scan flip-flop providing both scan and propagation delay testing

Abstract

A semiconductor integrated circuit device is provided with a selector that selects a normal operation signal or a circuit diagnosis input signal depending upon a first-mode input signal. A first latch and a second latch selectively execute one of (i) a scan mode for either holding or transmitting one of the normal operation signal and the circuit diagnosis input signal, selected by the selector depending upon a clock signal, and (ii) a long delay path function mode for transmitting a transmission signal irrespective of the clock signal, depending upon a second-mode input signal.

What is claimed is:  
     
       1. A semiconductor integrated circuit device for diagnosing logic circuit performance, the semiconductor integrated circuit device comprising: 
       a selector circuit that receives a first-mode input signal, and selects one of (i) a normal operation signal input into a logic circuit during a normal operation mode and (ii) a circuit diagnosis input signal input into the logic circuit during a test mode, in response to the first-mode input signal; and  
       a latch circuit including a logic gate for receiving and selectively holding and transmitting the one of the normal operation signal and the circuit diagnosis input signal, as a transmission signal, that has been selected by the selector circuit, the latch circuit:  
       receiving a clock signal having different first and second states and a second-mode input signal having different first and second states; and  
       selectively executing one of (i) a scan mode holding and transmitting, respectively, the transmission signal in response to the first and second states of the clock signal received, and (ii) a long delay path function mode transmitting the transmission signal irrespective of the first and second states of the clock signal, in response to only one of the first and second states of the second-mode input signal received, and including  
       at least one latch that includes the logic gate for selectively transmitting and holding the transmission signal,  
       a first controller selectively transmitting and interrupting the transmission signal depending upon whether the clock signal is in the first state or the second state when the second-mode input signal causes selection of the scan mode and transmitting the transmission signal to the logic gate when the second-mode input signal causes selection of the long delay path function mode, and  
       a second controller for selectively controlling transmission and holding of the transmission signal in the logic gate in response to whether the clock signal is in the first state or the second state.  
     
     
       2. The semiconductor integrated circuit device according to  claim 1 , wherein 
       the first controller has a first transmission gate and the transmission signal is transmitted to the logic gate through the first transmission gate, and  
       the second controller has a second transmission gate, and the logic gate selectively controls transmission and holding of the transmission signal in the logic gate by controlling the second transmission gate in response to whether the clock signal is in the first state or the second state.  
     
     
       3. The semiconductor integrated circuit device according to  claim 2 , wherein the first and second transmission gates are N-/P-channel transmission gates. 
     
     
       4. The semiconductor integrated circuit device according to  claim 2 , wherein the logic gate includes: 
       a first inverter which inverts a signal transmitted through the first controller to produce an inverted output;  
       a second inverter which inverts the output of the first inverter to produce an inverted signal and inputs the inverted signal to the first inverter through the second controller; and  
       a third transmission gate which interrupts input of the inverted signal to the first inverter when the second-mode input signal causes selection of the long delay path function mode.