Programmable differential D flip-flop

Abstract

A differential D flip-flop is disclosed including respective master and slave cells. The master cell comprises a first data set circuit and a first data store circuit. The data set circuit has a first differential input and a first differential output. The first data store circuit couples to the output of the first data set circuit. The cell further includes a differential clock circuit and a first current source for generating a fixed bias current in the master cell. The clock circuit having complementary clock inputs to alternatingly set and store data in the data set and data store circuits. The slave cell is formed substantially similar to the master cell, and includes a second differential input coupled to the first differential output of the master cell. The slave cell further includes a second current source for generating a second bias current in the slave cell, the second current source having programmable inputs for varying the slave cell bias current, thereby controlling the delay characteristic of the flip-flop.

What is claimed is:  
     
       1. A differential flip-flop including: 
       a master cell comprising  
       a first data set circuit having a first differential input and a first differential output,  
       a first data store circuit coupled to the output of the first data set circuit,  
       a differential clock circuit having complementary clock inputs to alternatingly set and store data in the data set and data store circuits, and  
       a first current source for generating a fixed bias current in the master cell; and  
       a slave cell formed substantially similar to the master cell, the slave cell having  
       a second differential input coupled to the first differential output of the master cell, and  
       a second current source for generating a second bias current in the slave cell, the second current source having programmable inputs for varying the slave cell bias current;  
       whereby the varying slave cell bias current provides control over the delay characteristics of the differential flip-flop.  
     
     
       2. A differential flip-flop according to  claim 1  wherein: 
       the second current source includes a plurality of binary-weighted current sources disposed in parallel to provide a selectable bias current.  
     
     
       3. A differential flip-flop according to  claim 1  wherein: 
       the master cell and slave cell are formed from a CMOS process.  
     
     
       4. A differential flip-flop for use in a timing system having a plurality of delay cells, each of the delay cells having delay load circuitry to generate a similar delay D, the flip-flop including: 
       a master cell having a fixed delay; and  
       a slave cell having a programmable input to vary the delay of the flip-flop output to track the similar delay D of each of the delay cells.  
     
     
       5. A differential flip-flop for use in a timing system according to  claim 4  wherein the master cell comprises: 
       a first data set circuit having a first differential input and a first differential output,  
       input load circuitry substantially matching the delay load circuitry,  
       a first data store circuit coupled to the output of the first data set circuit,  
       a differential clock circuit having complementary clock inputs to alternatingly set and store data in the data set and data store circuits, and  
       a first current source for generating a fixed bias current in the master cell.  
     
     
       6. A differential flip-flop for use in a timing system according to  claim 5  wherein the slave cell is formed similar to the master cell and further comprises: 
       a second differential input coupled to the first differential output of the master cell, and  
       a second current source for generating a second bias current in the slave cell, the second current source having programmable inputs for varying the slave cell bias current.  
     
     
       7. A differential flip-flop for use in a timing system according to  claim 6  wherein: 
       the second current source includes a plurality of binary-weighted current sources disposed in parallel to provide a selectable bias current.  
     
     
       8. A differential flip-flop for use in a timing system according to  claim 6  wherein: 
       the master cell and slave cell are formed from a CMOS process.  
     
     
       9. A timing circuit for use in automatic test equipment, the timing circuit including: 
       a delay line having a plurality of delay elements for generating timing signals, each of the delay elements having delay load circuitry to generate a similar delay D;  
       a differential data source for generating timing data values;  
       a differential system clock; and  
       a differential D flip-flop, the differential D flip-flop including  
       a master cell having a fixed delay and respective master data and master clock inputs, the master data input coupled to the data source and the master clock input coupled to the differential system clock, the master cell having a differential output; and  
       a slave cell having respective slave data and slave clock inputs, the slave data input coupled to the master cell differential output and the slave clock input inversely coupled to the differential system clock, the slave cell further including a slave differential output and a programmable input to vary the delay of the slave differential output to track the similar delay D of each of the delay cells.  
     
     
       10. A timing circuit for use in automatic test equipment according to  claim 9  wherein the master cell comprises: 
       a first data set circuit;  
       input load circuitry substantially matching the delay load circuitry;  
       a first data store circuit coupled to the input of the first data set circuit;  
       a differential clock circuit having complementary clock inputs to alternatingly set and store data in the data set and data store circuits; and  
       a first current source for generating a fixed bias current in the master cell.  
     
     
       11. A timing circuit for use in automatic test equipment according to claim a wherein the slave cell is formed similar to the master cell and further comprises: 
       a second differential input coupled to the first differential output of the master cell, and  
       a second current source for generating a second bias current in the slave cell, the second current source having programmable inputs for varying the slave cell bias current.  
     
     
       12. A timing circuit for use in automatic test equipment according to  claim 11  wherein: 
       the second current source includes a plurality of binary-weighted current sources disposed in parallel to provide a selectable bias current.  
     
     
       13. A timing circuit for use in automatic test equipment according to  claim 11  wherein: 
       the master cell and slave cell are formed from a CMOS process.