US6504887B1ExpiredUtility
Apparatus and method for an error minimizing phase locked loop
Priority: Aug 17, 1999Filed: Aug 17, 1999Granted: Jan 7, 2003
Est. expiryAug 17, 2019(expired)· nominal 20-yr term from priority
Inventors:Peter G. Khoury
H03L 7/091H04L 7/0334H03L 7/085
29
PatentIndex Score
0
Cited by
8
References
20
Claims
Abstract
A method of estimating a period and a time delay, or phase, of an input signal. A plurality of transition times {tilde over (t)} i are received, each transition time {tilde over (t)} i having a weight α{tilde over (γ)} i comprising a forgetting factor α and a weighting factor {tilde over (γ)} i . Upon receiving an N th transition time to and determining an N th weighting factor γ 0 , maximum likelihood estimates {circumflex over (T)} and {circumflex over (t)} φ of the period and the time delay, respectively, are calculated. The estimates are computed recursively, with {circumflex over (T)} depending upon α, γ 0 , t 0 , and a preceding maximum likelihood estimate {circumflex over (T)} of the period. The value of {circumflex over (t)} φ depends upon α, γ 0 , and t 0 . The estimates {circumflex over (T)} and {circumflex over (t)} φ also depend on sums S N−1 (n) =Σ i=−(N−2) 0 i n α −i{circumflex over (γ)} i . After the estimates {circumflex over (T)} and {circumflex over (t)} φ are computed, the sums are updated in anticipation of the next transition time. The method is preferably implemented electronically, resulting in a digital phase locked loop. The weighting factors allow the digital phase locked loop to lock onto a signal having absent transitions.
Claims
exact text as granted — not AI-modifiedI claim:
1. A method of estimating a period and a time delay of a signal, said method comprising the steps of:
a) selecting a forgetting factor α;
b) electrically receiving an N th transition time t 0 of said signal;
c) assigning an N th weighting factor γ 0 to said N th transition time t 0 ;
d) electronically computing a maximum likelihood estimate {circumflex over (T)} of said period using said N th transition time t 0 , said forgetting factor α, said N th weighting factor γ 0 , and a preceding maximum likelihood estimate {circumflex over (T)} of said period; and
e) electronically computing a maximum likelihood estimate {circumflex over (t)} φ of said time delay using said N th transition time t 0 , said forgetting factor α, and said N th weighting factor γ 0 .
2. The method of claim 1 , further comprising the steps of:
a) receiving N−1 transition times {tilde over (t)} i prior to said N th transition time t 0 ;
b) assigning a weighting factor {tilde over (γ)} i to each of said N−1 transition times {tilde over (t)} i ;
c) electronically storing sums S N−1 (n) for n=0, 1, and 2, wherein S N - 1 ( n ) = ∑ i = - ( N - 2 ) 0 i n a - i γ ~ i .
3. The method of claim 2 , wherein T ^ = T ~ + ( S N - 1 ( 0 ) - S N - 1 ( 1 ) ) γ 0 a ( S N - 1 ( 0 ) S N - 1 ( 2 ) - ( S N - 1 ( 1 ) ) 2 ) + ( S N - 1 ( 2 ) - 2 S N - 1 ( 1 ) + S N - 1 ( 0 ) ) γ 0 t 0 and t ^ φ = - ( S N - 1 ( 2 ) - 2 S N - 1 ( 1 ) + S N - 1 ( 0 ) ) γ 0 a ( S N - 1 ( 0 ) S N - 1 ( 2 ) - ( S N - 1 ( 1 ) ) 2 ) + ( S N - 1 ( 2 ) - 2 S N - 1 ( 1 ) + S N - 1 ( 0 ) ) γ 0 t 0 .
4. The method of claim 2 , further comprising the step of electronically computing sums S N (n) for n=0, 1, and 2 using the following formulas:
S N (0) =γ 0 +αS N−1 (0) ,
S N (1) =α( S N−1 (1) −S N−1 (0) ),
and
S N (2) =α( S N−1 (2) −2 S N−1 (1) +S N−1 (0) ).
5. A method of estimating a period and a time delay of a signal, said method comprising the steps of:
a) electrically receiving an N th transition time t 0 of said signal,
b) electronically computing a maximum likelihood estimate {circumflex over (T)} of said period using said N th transition time t 0 and a preceding maximum likelihood estimate {tilde over (T)} of said period, and
c) electronically computing an N th maximum likelihood estimate {circumflex over (t)} φ of said time delay using said N th transition time t 0 .
6. The method of claim 5 , wherein T ^ = T ~ + 6 N ( N + 1 ) t 0 and t ^ φ = - 2 ( 2 N - 1 ) N ( N + 1 ) t 0 .
7. The method of claim 5 , further comprising the step of selecting a forgetting factor α, and wherein said estimates {circumflex over (T)} and {circumflex over (t)} φ depend upon said forgetting factor α.
8. The method of claim 7 , wherein T ^ = T ~ + [ ( N - 1 ) a N + 2 - ( 3 N - 2 ) a N + 1 + ( 3 N - 1 ) a N + a 2 - 2 a + 1 a 2 N - N 2 a N + 1 + 2 ( N 2 - 1 ) a N - N 2 a N - 1 + 1 ] t 0 and t ^ φ = [ - ( N - 1 ) 2 a N + 2 + ( 3 N - 4 ) Na N + 1 - ( 3 N + 1 ) ( N - 1 ) a N + N 2 a N - 1 + a 2 - 1 a 2 N - N 2 a N + 1 + 2 ( N 2 - 1 ) a N - N 2 a N - 1 + 1 ] t 0 .
9. The method of claim 7 , wherein
{circumflex over (T)}={tilde over (T)} +(1−α) 2 t 0 and {circumflex over (t)} φ =−(1−α 2 ) t 0 .
10. The method of claim 7 , further comprising the step of receiving an N th weighting factor γ 0 , and wherein said estimates {circumflex over (T)} and {circumflex over (t)} φ depend upon said N th weighting factor γ 0 .
11. A digital phase locked loop for locking on to an input signal, said phase locked loop comprising:
a) a receiving means for receiving said input signal;
b) a means for determining (i) an N th transition time t 0 of said input signal, and (ii) an N th weighting factor γ 0 to said transition time t 0 ;
c) a circuit for computing maximum likelihood estimates {circumflex over (T)} and {circumflex over (t)} φ of a period and a time delay, respectively, of said input signal, wherein said circuit computes said estimate {circumflex over (T)} using a forgetting factor α, said N th weighting factor γ 0 , said N th transition time t 0 , and a preceding maximum likelihood estimate {tilde over (T)} of said period; and wherein said circuit computes said estimate {circumflex over (t)} φ using said forgetting factor α, said N th weighting factor γ 0 , and said N th transition time t 0 ; and
d) an electrical output responsive to said circuit, for sending an output signal characterized by said estimates {circumflex over (T)} and {circumflex over (t)} φ .
12. The digital phase locked loop of claim 11 , wherein said circuit records values of sums S N−1 (n) for n=0, 1, and 2, wherein S N - 1 ( n ) = ∑ i = ( N - 2 ) 0 i n a - i γ ~ i ,
{tilde over (γ)} i being a weighting factor of an i th transition time prior to said N th transition time t 0 .
13. The digital phase locked loop of claim 12 , wherein said circuit computes said estimates {circumflex over (T)} and {circumflex over (t)} φ according to the following formulas: T ^ = T ~ + ( S N - 1 ( 0 ) - S N - 1 ( 1 ) ) γ 0 a ( S N - 1 ( 0 ) S N - 1 ( 2 ) - ( S N - 1 ( 1 ) ) 2 ) + ( S N - 1 ( 2 ) - 2 S N - 1 ( 1 ) + S N - 1 ( 0 ) ) γ 0 t 0 and t ^ φ = - ( S N - 1 ( 2 ) - 2 S N - 1 ( 1 ) + S N - 1 ( 0 ) ) γ 0 a ( S N - 1 ( 0 ) S N - 1 ( 2 ) - ( S N - 1 ( 1 ) ) 2 ) + ( S N - 1 ( 2 ) - 2 S N - 1 ( 1 ) + S N - 1 ( 0 ) ) γ 0 t 0 .
14. The digital phase locked loop of claim 12 , wherein said circuit computes sums S N (n) for n=0, 1, and 2 according to the following formulas:
S N (0) =γ 0 +αS N−1 (0) ,
S N (1) =α( S N−1 (1) −S N−1 (0) ),
and
S N (2) =α( S N−1 (2) −2 S N−1 (1) +S N−1 (0) ).
15. A digital phase locked loop for locking on to an input signal, said phase locked loop comprising:
a) a receiving means for receiving said input signal;
b) a means for determining an N th transition time t 0 of said input signal;
c) a circuit for computing maximum likelihood estimates {circumflex over (T)} and {circumflex over (t)} φ of a period and a time delay, respectively, of said input signal, wherein said circuit computes said estimate {circumflex over (T)} using said N th transition time t 0 and a preceding maximum likelihood estimate {tilde over (T)} of said period; and wherein said circuit computes said estimate {circumflex over (t)} φ using said N th transition time t 0 ; and
d) an electrical output responsive to said circuit, for sending an output signal characterized by said estimates {circumflex over (T)} and {circumflex over (t)} φ .
16. The digital phase locked loop of claim 15 , wherein T ^ = T ~ + 6 N ( N + 1 ) t 0 and t ^ φ = - 2 ( 2 N - 1 ) N ( N + 1 ) t 0 .
17. The digital phase locked loop of claim 15 , wherein said circuit computes said estimates {circumflex over (T)} and {circumflex over (t)} φ using a forgetting factor α.
18. The digital phase locked loop of claim 17 , wherein T ^ = T ~ + [ ( N - 1 ) a N + 2 - ( 3 N - 2 ) a N + 1 + ( 3 N - 1 ) a N + a 2 - 2 a + 1 a 2 N - N 2 a N + 1 + 2 ( N 2 - 1 ) a N - N 2 a N - 1 + 1 ] t 0 and t ^ φ = [ - ( N - 1 ) 2 a N + 2 + ( 3 N - 4 ) Na N + 1 - ( 3 N + 1 ) ( N - 1 ) a N + N 2 a N - 1 + a 2 - 1 a 2 N - N 2 a N + 1 + 2 ( N 2 - 1 ) a N - N 2 a N - 1 + 1 ] t 0 .
19. The digital phase locked loop of claim 17 , wherein
{circumflex over (T)}={tilde over (T)} +(1−α) 2 t 0 and {circumflex over (t)} φ =−(1−α 2 ) t 0 .
20. The digital phase locked loop of claim 17 , further comprising a means for determining an N th weighting factor γ 0 of said N th transition time t 0 ;
wherein said circuit computes said estimates {circumflex over (T)} and {circumflex over (t)} φ using said N th weighting factor γ 0 .Cited by (0)
No later patents cite this yet.
References (0)
No backward citations on record.