Semiconductor package having stacked dice and leadframes and method of fabrication

Abstract

A semiconductor package, and a method for fabricating the package are provided. The package includes a plastic body, and a pair of stacked semiconductor dice encapsulated in the plastic body, and wire bonded to separate leadframe segments. A first leadframe segment includes lead fingers configured to support a first semiconductor die of the stacked pair, and to form terminal leads of the package. A second leadframe segment is attached to the first leadframe segment, and includes lead fingers that support a second semiconductor die of the stacked pair. The lead fingers of the second leadframe are in physical and electrical contact with the leadfingers of the first leadframe. In addition, tip portions of the lead fingers of the first leadframe segment are staggered relative to tip portions of the lead fingers of the second leadframe segment to provide space for bond wires. The lead fingers support the dice during encapsulation, and also provide a heat conductive path for transferring heat from the dice during operation. The package can be constructed using lead-on-chip leadframes and conventional semiconductor packaging equipment.

What is claimed is:  
     
       1. A method for fabricating a semiconductor package comprising: 
       providing a first leadframe comprising a plurality of first leads;  
       attaching and wire bonding a first semiconductor die to the first leads;  
       providing a second leadframe comprising a plurality of second leads;  
       attaching and wire bonding a second semiconductor die to the second leads;  
       forming a metal layer around the first leads and the second leads to attach the first leadframe to the second leadframe with the first leads in physical and electrical contact with the second leads; and  
       forming the first leads into terminal leads for the package.  
     
     
       2. The method of  claim 1  wherein the forming the metal layer step comprises a plating process. 
     
     
       3. The method of  claim 1  wherein the first leadframe and the second leadframe comprise lead-on-chip leadframes. 
     
     
       4. A method for fabricating a semiconductor package comprising: 
       providing a first leadframe comprising a plurality of first leadfingers comprising first tip portions and first terminal portions;  
       attaching a first die to the first tip portions;  
       wire bonding the first die to the first tip portions;  
       providing a second leadframe comprising a plurality of second leadfingers comprising second tip portions and second terminal portions;  
       attaching a second die to the second tip portions;  
       wire bonding the second die to the second tip portions;  
       welding, brazing, or soldering the first leadframe to the second leadframe with theitirst terminal portions and the second terminal portions in physical and electrical contact;  
       forming metal layers on the first leadfingers and on the second leadfingers to rigidify the physical and electrical contact; and  
       forming the first terminal portions into terminal leads for the package.  
     
     
       5. The method of  claim 4  wherein the first tip portions and the second tip portions are staggered following the welding, brazing or soldering step to provide spaces for bond wires. 
     
     
       6. The method of  claim 4  wherein the metal layers comprise a metal selected from the group consisting of solder, copper, silver, nickel, and gold. 
     
     
       7. The method of  claim 4  further comprising forming conductive adhesive layers between the first terminal portions and the second terminal portions to rigidify the physical and the: electrical contact. 
     
     
       8. The method of  claim 4  further comprising encapsulating the first die, the second die, the first terminal portions and the second terminal portions in a plastic body with the terminal leads extending therefrom. 
     
     
       9. A method for fabricating a semiconductor package comprising: 
       providing a first die and a second die;  
       providing a first leadframe comprising a plurality of first leadfingers comprising first die attach surfaces and first wire bonding surfaces;  
       attaching the first die to the first die attach surfaces;  
       wire bonding the first die to the first wire bonding surfaces;  
       providing a second leadframe comprising a plurality of second leadfingers comprising second die attach surfaces and second wire bonding surfaces;  
       attaching the second die to the second die attach surfaces;  
       wire bonding the second did to the second wire bonding surfaces;  
       forming conductive adhesive layers between the first leadfingers and the second leadfingers;  
       forming metal layers on the first leadfingers and on the second leadfingers; and  
       forming the first leadfingers into terminal leads for the package.  
     
     
       10. The method of  claim 9  wherein the first leadframe and the second leadframe comprise lead-on-chip leadframes. 
     
     
       11. The method of  claim 9  wherein the metal layers comprise a metal selected from the group consisting of solder, copper, silver, nickel, and gold.