Page address look-up range ram

Abstract

A Page Address Look-up Range RAM is disclosed which allows for individual comparisons to be made on a number of consecutive addresses. The upper bits of the bus address 410 (often representing a “page”) are compared against one or more reference registers 430-437 to yield one or more “match_high”s. The lower bits of the same bus address 420 are used to look-up the value of “match_low” in a Page Look-Up RAM 440, the bit of interest corresponding to the particular “match-high” reference register i.e. 430. If both the “match_high” and “match_low” events are true, or=1, then the bus address has matched and should cause the event, otherwise not. The most cost effective implementations will have a Look-up RAM 440 with a width of a multiple of 8. This will allow comparison of the bus address against a multiple of individual pages.

What is claimed is:  
     
       1. A method of causing an event, comprising the steps of: 
       providing an address, having an upper bit portion and a lower bit portion;  
       comparing said upper bit portion of said address against one or more reference registers for yielding one or more “match-high's”;  
       locating said lower bit portion of said address within a memory look-up table for yielding one or more “match-lows”;  
       causing the event upon the occurrence of both the “match-high” and “match-low” being true;  
       wherein said lower bit portion indicates a word address in said look-up table;  
       wherein said address has N bits, said word address has P bits and wherein said one or more reference registers comprises P particular reference registers; and  
       wherein one of said P particular reference registers correspond to one of said bits of said P bit word address.  
     
     
       2. The method according to  claim 1  wherein upon said one corresponding bit of said P bit word address equaling 1, said match_low corresponding to said bit is true. 
     
     
       3. The method according to  claim 1 , wherein said upper bit portion of said address comprises N−L bits where L is the number of bits in said lower bit portion of said address. 
     
     
       4. The method according to  claim 3  wherein said memory look-up table comprises 2 L  entries and is P bits wide. 
     
     
       5. The method according to  claim 3  wherein said reference register comprises (N−L) bits. 
     
     
       6. The method according to  claim 3  wherein said upper portion of said address comprises (N−L) bits. 
     
     
       7. The method according to  claim 1  wherein there are more than one “match_high”s and “match_low”s.