Method of manufacturing semiconductor device as well as reticle and wafer used therein

Abstract

A predetermined reticle is used for sequentially irradiating (giving a shot of) an exposure light onto a negative resist. In the negative resist the region irradiated with the exposure light remains as a resist pattern. The exposure light is not irradiated onto the negative resist in the wafer outer peripheral region. After that, a negative resist pattern is formed by carrying out a development process and, by using this as a mask, etching is carried out on the first conductive layer and, thereby, the first metal wire layer is formed. Since no resist pattern is formed in the wafer outer peripheral region, the first conductive layer does not remain. Thereby, a semiconductor device wherein a conductive layer is prevented from scattering off at the time of the dicing of the wafer can be gained.

What is claimed is:  
     
       1. A method of manufacturing a semiconductor device having: 
       a step of forming a conductive layer on a wafer as semiconductor substrate;  
       a resist application step of applying a resist on said conductive layer;  
       an exposure step of sequentially irradiating an exposure light onto said resist located in a plurality of chip formation regions for forming, respectively, semiconductor chips in said wafer via a predetermined reticle;  
       a development step of forming a resist pattern for patterning said conductive layer by developing said resist after said exposure step; and  
       a step of forming a conductive region by etching said conductive layer using said resist pattern as a mask, wherein  
       said exposure step comprises a step of providing a resist-free region which is cut by dicing and is provided in a region outside of the chip formation regions and located in a wafer outermost periphery adjacent said chip formation regions.  
     
     
       2. The method of manufacturing a semiconductor device according to  claim 1 , wherein 
       a negative resist is used as said resist in said resist application step; and  
       no exposure light in said exposure step irradiates the region outside of the chip formation regions located in said outermost periphery.  
     
     
       3. The method of manufacturing a semiconductor device according to  claim 1 , wherein 
       in said exposure step, a spot of said exposure light irradiates along a border between the chip formation regions located adjacent said outermost periphery and the region outside of the chip formation region located in said outermost periphery after said exposure light sequentially irradiates said resist located in said plurality of chip formation regions.  
     
     
       4. The method of manufacturing a semiconductor device according to  claim 1 , wherein 
       a dummy reticle is used during an exposure in said exposure step during which no pattern is formed on the region outside of the chip formation regions located in said outermost periphery.  
     
     
       5. The method of manufacturing a semiconductor device according to  claim 1 , wherein 
       during said exposure step, said predetermined reticle provides peripheral dicing line pattern regions having a pattern width for providing regions to be cut by dicing, said peripheral dicing line pattern regions are formed along the outermost periphery, and  
       during sequential exposures using said predetermined reticle, in one exposure and in an immediately following exposure, the exposures are carried out in positions wherein said peripheral dicing line pattern regions overlap at least partially in a plane.  
     
     
       6. The method of manufacturing a semiconductor device according to  claim 5 , wherein 
       said peripheral dicing line pattern region have substantially equal widths in said predetermined reticle, and  
       in one exposure and in an immediately following exposure, the exposures are carried out in positions wherein said peripheral dicing line pattern regions completely overlap in a plane.  
     
     
       7. The method of manufacturing a semiconductor device according to  claim 6 , wherein 
       the resist pattern is substantially not formed in said peripheral dicing line pattern regions.