Backgate biased synchronizing latch

Abstract

An apparatus having a latch core, where the latch core has a plurality of devices and at least one of the devices has a back gate bias net. A bias voltage circuit is coupled to the back gate bias net. The apparatus may further comprise back to back inverters where each inverter output is coupled to the other inverter input. The inverters may further comprise a PFET transistor and an NFET transistor, where the PFET transistors have a back gate bias net. The inverters may further comprise a PFET transistor and an NFET transistor, the NFET transistors having a back gate bias net. The inverters may further comprise a PFET transistor and an NFET transistor, the NFET transistors and the PFET transistors having a back gate bias net. The bias voltage circuit may be further configured to apply a bias voltage when a metastability may occur. The bias voltage circuit may further comprise a NAND gate.

What is claimed is:  
     
       1. An apparatus, comprising: 
       a latch circuit having an input of a first inverter coupled to an output of a second inverter at a first node, and, an input of said second inverter coupled to an output of said first inverter at a second node, said latch circuit at a first stable state when said first node is at a first voltage and said second node is at second voltage, said latch circuit at a second stable state when said first node is at said second voltage and said second node is at said first voltage, said latch circuit having a metastable state that is approached as said first and said second nodes approach a third voltage between said first and second voltages, said first and second inverters each having a transistor with a back gate bias node that receives a back gate bias voltage, said back gate bias voltage provided by a logic circuit in response to an input applied to said latch circuit, wherein said back gate bias voltage increases the gain of said transistors so as to avoid said metastable state as a result of said input being applied to said latch circuit, said input being a data signal value and a clock signal value that could have been transitioned to such that the transition to said data signal value was sufficiently proximate to the transition to said clock signal value so as to cause said metastable state, said latch circuit designed to latch a value of said data signal on a said clock signal transition.  
     
     
       2. The apparatus of  claim 1  wherein said transistors are PFET transistors. 
     
     
       3. The apparatus of  claim 2  wherein said PFET transistors are implemented within a n-well. 
     
     
       4. The apparatus of  claim 2  further comprising a clamp across one of said PFET transistors. 
     
     
       5. The apparatus of  claim 1  wherein said logic gate is a NAND gate. 
     
     
       6. The apparatus of  claim 1  wherein said back gate bias voltage is further provided by said logic gate in response to said input and a voltage on one of said nodes. 
     
     
       7. The apparatus of  claim 1  wherein another data signal value can be latched on a rising said clock signal transition. 
     
     
       8. The apparatus of  claim 1  further comprising a reset signal that resets said latch circuit to one of said stable states. 
     
     
       9. A method, comprising: 
       a) offering an input to a latch circuit, said latch circuit having an input of a first inverter coupled to an output of a second inverter at a first node, and, an input of said second inverter coupled to an output of said first inverter at a second node, said latch circuit at a first stable state when said first node is at a first voltage and said second node is at second voltage, said latch circuit at a second stable state when said first node is at said second voltage and said second node is at said first voltage, said latch circuit having a metastable state that is approached as said first and said second nodes approach a third voltage between said first and second voltages, a first transistor within said first inverter and a second transistor within said second inverter; and  
       b) increasing the gain of said transistors, when said input corresponds to a cause of said metastable state, by providing a back gate bias to said transistors with a logic circuit that recognizes the presence of said input, said input being a data signal value and a clock signal value that could have been transitioned to such that the transition to said data signal value was sufficiently proximate to the transition to said clock signal value so as to cause said metastable state, said latch circuit designed to latch a value of said data signal on a said clock signal transition.  
     
     
       10. The method of  claim 9  wherein said transistors are PFET transistors. 
     
     
       11. The method of  claim 10  wherein said PFET transistors are implemented within a n-well. 
     
     
       12. The method of  claim 9  wherein said back gate bias voltage is further provided by said logic gate in response to said input and a voltage on one of said nodes. 
     
     
       13. The method of  claim 9  further comprising latching another data signal value on a rising said clock signal transition. 
     
     
       14. The method of  claim 9  further comprising resetting said latch circuit to one of said stable states.