Flash memory device

Abstract

A flash memory device capable of compensating the decrease of a threshold voltage of an unselected cell due to the drain coupling caused by a drain voltage supplied to a bit line of a selected cell is disclosed. The flash memory device provides a ground voltage to a source line of the selected cell while supplying a preset voltage to a source line of the unselected cell. The flash memory device employs a decoding unit for supplying a program voltage to a word line selected from a cell array based on a global word line signal, a local word line signal and a predecoder signal. The decoding unit also provides a ground voltage to a source line corresponding to the selected word line in response to a sector program signal and an inverted sector program signal and inputs a preset voltage higher than the ground voltage to source lines of unselected cells.

What is claimed is:  
     
       1. A flash memory device comprising: 
       a flash memory cell array including a plurality of cellblocks, each cellblock having a multiplicity of cells;  
       a multiplexor, said multiplexor selecting a bit line among a plurality of bit lines of the cell array; and  
       decoding means, said decoding means  
       supplying a program voltage to a word line selected among a plurality of word lines of the cell array based on a global word line signal, a local word line signal and a predecoder signal,  
       providing a ground voltage to a source line of a cellblock including the selected word line in response to a sector program signal and an inverted sector program signal, and  
       inputting a preset voltage higher than the ground voltage to source lines of unselected cellblocks.  
     
     
       2. The flash memory device according to  claim 1 , said decoding means including a plurality of decoding blocks, wherein each decoding block has a multiplicity of decoding circuits. 
     
     
       3. The flash memory device according to  claim 2 , wherein a number of the decoding blocks equals a number of the cellblocks. 
     
     
       4. The flash memory device according to  claim 3 , said decoding means further including: 
       switching means for adjusting the potential of a first node in response to the global word line signal and a first control signal;  
       means for selecting the word line based on the predecoder signal and the potential of the first node and providing the local word line signal to the word line;  
       means for inverting the first control signal; and a transmission gate for providing an output signal of said means for inverting to the source line of the cellblock in response to the sector program signal and the inverted sector program signal.  
     
     
       5. The flash memory device according to  claim 1 , said decoding means further including means for switching and adjusting the potential of a first node in response to the global word line signal and a first control signal. 
     
     
       6. The flash memory device according to  claim 5 , said decoding means further including means for selecting the word line based on the predecoder signal and the potential of the first node and providing the local word line signal to the word line. 
     
     
       7. The flash memory device according to  claim 5 , said decoding means further including means for inverting the first control signal. 
     
     
       8. The flash memory device according to  claim 7 , said decoding means further including a transmission gate for providing an output signal of the inverting means to the source line of the cellblock in response to the sector program signal and the inverted sector program signal. 
     
     
       9. The flash memory device according to  claim 1 , said decoding means further including: 
       switching means for adjusting the potential of a first node in response to the global word line signal and a first control signal;  
       means for selecting the word line based on the predecoder signal and the potential of the first node and providing the local word line signal to the word line;  
       means for inverting the first control signal; and  
       a transmission gate for providing an output signal of said means for inverting to the source line of the cellblock in response to the sector program signal and the inverted sector program signal.  
     
     
       10. The flash memory device according to  claim 9 , said word line selecting means further including: 
       first switching means for transferring the local word line signal to the selected word line in response to the potential of the first node,  
       second switching means for adjusting the potential of the selected word line according to the output signal of the inverting means, and  
       third switching means for controlling the potential of the selected word line depending on the predecoder signal.  
     
     
       11. A method of programming a flash memory device having a flash memory cell array including a plurality of cellblocks, each cellblock having a multiplicity of cells, a multiplexor, wherein said multiplexor selects a bit line among a plurality of bit lines of the cell array; and a decoding unit, said method comprising the steps of: 
       supplying a program voltage to a word line selected among a plurality of word lines of the cell array based on a global word line signal, a local word line signal and a predecoder signal,  
       providing a ground voltage to a source line of a cellblock including the selected word line in response to a sector program signal and an inverted sector program signal, and  
       inputting a preset voltage higher than the ground voltage to a plurality of source lines of unselected cellblocks.  
     
     
       12. The method according to  claim 11 , wherein a high voltage of about 9 V is supplied through the first global word line signal and the local word line signal. 
     
     
       13. The method according to  claim 12 , wherein a voltage of approximately 2 V is supplied to the source lines of the unselected cells. 
     
     
       14. The method according to  claim 11 , wherein a voltage of approximately 2 V is supplied to the source lines of the unselected cells.