Semiconductor device using a shallow trench isolation

Abstract

In a MOS transistor using shallow trench isolation, a pattern of an element formation region has a shape of a modified hexagon in which a hexagon is compressed into a shape like a rhombus in a direction perpendicular to an extension direction of a gate electrode wiring. The pattern of element formation region is constructed as described above, so that an element formation region is formed in a lager current path in a corner device. Thus, a lowering of a threshold voltage (a short channel effect) due to the comer device can be restricted without increasing a width of the gate electrode wiring.

What is claimed as new and is desired to be secured by Letters Patent of the United States is:  
     
       1. A semiconductor device comprising: 
       an element isolation region of shallow trench isolation type, the element isolation region having a trench formed in a surface region of a semiconductor substrate, and in which an isolation film is formed;  
       a gate electrode wiring;  
       a bit line; and  
       element forming regions formed in the surface region of the semiconductor substrate isolated from each other by said element isolation region, each of the element forming regions having a pattern with a width at a central portion of the element forming region and with a width at both edge portions of the element forming region narrower than the width at the central portion, wherein  
       one of a source diffusion layer and a drain diffusion layer of a MOS transistor is formed in the central portion of the element forming region, said one of the source diffusion layer and the drain diffusion layer of the MOS transistor is electrically connected to the bit line,  
       the other of the source diffusion layer and the drain diffusion layer of the MOS transistor is formed in the edge portions of the element forming region, said other of the source diffusion layer and the drain diffusion layer of the MOS transistor is electrically connected to a storage node of a capacitor, and  
       the source diffusion layer and the drain diffusion layer are separated from each other by said gate electrode wiring in a top view.  
     
     
       2. The semiconductor device according to  claim 1 , wherein a distance between a cross-point of an interface, in the top view, of the element isolation region and the element forming region and one side of the gate electrode wiring and a cross-point of the interface of the element isolation region and the element forming region and the other side of the gate electrode wiring is longer than a shortest distance between said one side and said other side of the gate electrode wiring. 
     
     
       3. The semiconductor device according to  claim 1 , wherein a portion of the semiconductor substrate at a side wall of said trench is not covered with the isolation film to form an exposed trench portion and said gate electrode wiring is formed on said exposed trench portion. 
     
     
       4. The semiconductor device according to  claim 1 , wherein said element forming region has a formation region in which a stacked capacitor constituting said capacitor is formed. 
     
     
       5. The semiconductor device according to  claim 2 , wherein a portion of the semiconductor substrate at a side wall of said trench is not covered with the isolation film to form an exposed trench portion and said gate electrode wiring is formed on said exposed trench portion. 
     
     
       6. The semiconductor device according to  claim 2 , wherein said element forming region has a formation region in which a stacked capacitor constituting said capacitor is formed. 
     
     
       7. The semiconductor device according to  claim 1 , wherein said pattern and said gate electrode wiring obliquely cross each other. 
     
     
       8. A semiconductor device comprising: 
       an element isolation region of shallow trench isolation type, the element isolation region having a trench formed in a surface region of a semiconductor substrate, and in which an isolation film is formed;  
       a gate electrode wiring;  
       a bit line; and  
       element forming regions formed in the surface region of the semiconductor substrate isolated from each other by said element isolation region, each of the element forming regions having a pattern with a width at a central portion of the element forming region and with a width at both edge portions of the element forming region narrower than the width at the central portion, wherein  
       one of a source diffusion layer and a drain diffusion layer of a MOS transistor is formed in the central portion of the element forming region, said one of the source diffusion layer and the drain diffusion layer of the MOS transistor is electrically connected to the bit line,  
       the other of the source diffusion layer and the drain diffusion layer of the MOS transistor is formed in the edge portions of the element forming region, said other of the source diffusion layer and the drain diffusion layer of the MOS transistor is electrically connected to a storage node of a capacitor, and  
       the source diffusion layer and the drain diffusion layer are separated from each other by said gate electrode wiring when observed in a top view,  
       a distance between a cross-point of an interface, in the top view, of the element isolation region and the element forming region and one side of the gate electrode wiring and a cross-point of the interface of the element isolation region and the element forming region and the other side of the gate electrode wiring is longer than a shortest distance between the said one side and said other side of the gate electrode wiring, and  
       the element forming region exists in a part of the surface region, and said part is defined by lines by connecting in the top view the cross-point of the interface of the element isolation region and the element forming region and said one side of the gate electrode wiring and a cross-point of the interface of the element isolation region and the element forming region and said other side of the gate electrode wiring.  
     
     
       9. The semiconductor device according to  claim 8 , wherein a portion of the semiconductor substrate at a side wall of said trench is not covered with the isolation film to form an exposed trench portion and said gate electrode wiring is formed on said exposed trench portion. 
     
     
       10. The semiconductor device according to  claim 8 , wherein said element forming region has a formation region in which a stacked capacitor constituting said capacitor is formed. 
     
     
       11. The semiconductor device according to  claim 8 , wherein a portion of the semiconductor substrate at a side wall of said trench is not covered with the isolation film to form an exposed trench portion and said gate electrode wiring is formed on said exposed trench portion. 
     
     
       12. The semiconductor device according to  claim 8 , wherein said element forming region has a formation region in which a stacked capacitor constituting said capacitor is formed. 
     
     
       13. The semiconductor device according to  claim 8 , wherein said pattern and said gate electrode wiring obliquely cross each other. 
     
     
       14. A semiconductor device comprising: 
       an element isolation region of shallow trench isolation type, the element isolation region having a trench formed in a surface region of a semiconductor substrate, and in which an isolation film is formed;  
       a gate electrode wiring;  
       a bit line; and  
       element forming regions formed in the surface region of the semiconductor substrate isolated from each other by said element isolation region, each of the element forming regions having a pattern with a width at a central portion of the element forming region and with a width at both edge portions of the element forming region narrower than the width at the central portion, wherein  
       one of a source diffusion layer and a drain diffusion layer of a MOS transistor is formed in the central portion of the element forming region, said one of the source diffusion layer and the drain diffusion layer of the MOS transistor is electrically connected to the bit line,  
       the other of the source diffusion layer and the drain diffusion layer of the MOS transistor is formed in the edge portions of the element forming region, said other of the source diffusion layer and the drain diffusion layer of the MOS transistor is electrically connected to a storage node of a capacitor,  
       the source diffusion layer and the drain diffusion layer are separated from each other by said gate electrode wiring when observed in a top view,  
       a portion of the element forming region overlaps with the gate electrode wiring and has a first pair of sides and a second pair of sides, the first pair of sides comprises a first side and a second side extending in a direction of the gate electrode wiring, the second pair of sides comprises a first and a second side crossing the first and second sides of the first pair of sides, and  
       the first side of the second pair of sides is longer than the second side of the second pair of sides, and a length of the second side of the second pair of sides has a shortest distance formed between the first side and the second side of the first pair of sides.  
     
     
       15. The semiconductor device according to  claim 14 , wherein a portion of the semiconductor substrate at a side wall of said trench is not covered with the isolation film to form an exposed trench portion and said gate electrode wiring is formed on said exposed trench portion. 
     
     
       16. The semiconductor device according to  claim 14 , wherein said element forming region has a formation region in which a stacked capacitor constituting said capacitor is formed. 
     
     
       17. The semiconductor device according to  claim 14 , wherein said pattern and said gate electrode wiring obliquely cross each other. 
     
     
       18. A semiconductor device comprising: 
       an element isolation region of shallow trench isolation type, the element isolation region having a trench formed in a surface region of a semiconductor substrate, and in which an isolation film is formed;  
       a gate electrode wiring;  
       a bit line; and  
       element forming regions formed in the surface region of the semiconductor substrate isolated from each other by said element isolation region, each of the element forming regions having a pattern with a width at a central portion of the element forming region and with a width at both edge portions of the element forming region narrower than the width at the central portion; wherein  
       one of a source diffusion layer and a drain diffusion layer of a MOS transistor is formed in the central portion of the element forming region, said one of the source diffusion layer and the drain diffusion layer of the MOS transistor is electrically connected to the bit line,  
       the other of the source diffusion layer and the drain diffusion layer of the MOS transistor is formed in the edge portions of the element forming region, said other of the source diffusion layer and the drain diffusion layer of the MOS transistor is electrically connected to a storage node of a capacitor,  
       the source diffusion layer and the drain diffusion layer are separated from each other by said gate electrode wiring when observed in a top view,  
       a portion of the element forming region overlaps with the gate electrode wiring and has a first pair of sides and a second pair of sides, the first pair of sides comprises a first side and a second side extending in a direction of the gate electrode wiring, the second pair of sides comprises a first and a second side crossing the first and second sides of the first pair of sides, and  
       the first and second sides of the first pair of sides are different in length from each other and the first and second sides of the second pair of sides are different in length form each other, so that the portion of the element forming region overlapping with the gate electrode wiring has a shape of a trapezoid.  
     
     
       19. The semiconductor device according to  claim 18 , wherein a portion of the semiconductor substrate at a side wall of said trench is not covered with the isolation film to form an exposed trench portion and said gate electrode wiring is formed on said exposed trench portion. 
     
     
       20. The semiconductor device according to  claim 18 , wherein said element forming region has a formation region in which a stacked capacitor constituting said capacitor is formed. 
     
     
       21. The semiconductor device according to  claim 18 , wherein said pattern and said gate electrode wiring obliquely cross each other. 
     
     
       22. A semiconductor device comprising: 
       an element isolation region of shallow trench isolation type, the element isolation region having a trench formed in a surface region of a semiconductor substrate, and in which an isolation film is formed;  
       a gate electrode wiring;  
       a bit line; and  
       element forming regions formed in the surface region of the semiconductor substrate isolated from each other by said element isolation region, each of the element forming regions having a pattern with a width at a central portion of the element forming region and with a width at both edge portions of the element forming region narrower than the width at the central portion, wherein  
       one of a source diffusion layer and a drain diffusion layer of a MOS transistor is formed in the central portion of the element forming region, said one of the source diffusion layer and the drain diffusion layer of the MOS transistor is electrically connected to the bit line,  
       the other of the source diffusion layer and the drain diffusion layer of the MOS transistor is formed in the edge portions of the element forming region, said other of the source diffusion layer and the drain diffusion layer of the MOS transistor is electrically connected to a storage node of a capacitor,  
       the source diffusion layer and the drain diffusion layer are separated from each other by said gate electrode wiring when observed in a top view, and  
       one of both sides of the element forming region extending in the direction crossing the gate electrode wiring is a shape of a straight line.  
     
     
       23. The semiconductor device according to  claim 22 , wherein a portion of the semiconductor substrate at a side wall of said trench is not covered with the isolation film to form an exposed trench portion and said gate electrode wiring is formed on said exposed trench portion. 
     
     
       24. The semiconductor device according to  claim 22 , wherein said element forming region has a formation region in which a stacked capacitor constituting said capacitor is formed. 
     
     
       25. The semiconductor device according to  claim 22 , wherein said pattern and said gate electrode wiring obliquely cross each other. 
     
     
       26. A semiconductor device comprising: 
       an element isolation region of shallow trench isolation type, the element isolation region having a trench formed in a surface region of a semiconductor substrate, and in which an isolation film is formed;  
       a gate electrode wiring;  
       a bit line; and  
       element forming regions formed in the surface region of the semiconductor substrate isolated from each other by said element isolation region, each of the element forming regions having a pattern with a width at both edge portions of the element forming region and with a width at both edge portions of the element forming region narrower than the width at the central portion, wherein  
       one of a source diffusion layer and a drain diffusion layer of a MOS transistor is formed in the central portion of the element forming region, said one of the source diffusion layer and the drain diffusion layer of the MOS transistor is electrically connected to the bit line,  
       the other of the source diffusion layer and the drain diffusion layer of the MOS transistor is formed in the edge portions of the element forming region, said other of the source diffusion layer and the drain diffusion layer of the MOS transistor is electrically connected to a storage node of a capacitor,  
       the source diffusion layer and the drain diffusion layer are separated from each other by said gate electrode wiring when observed in a top view, and  
       the width of the central portion of the element forming region is larger than that of each of said both edge portions of the element forming region.  
     
     
       27. The semiconductor device according to  claim 26 , wherein a portion of the semiconductor substrate at a side wall of said trench is not covered with the isolation film to form an exposed trench portion and said gate electrode wiring is formed on said exposed trench portion. 
     
     
       28. The semiconductor device according to  claim 26 , wherein said element forming region has a formation region in which a stacked capacitor constituting said capacitor is formed. 
     
     
       29. The semiconductor device according to  claim 26 , wherein said pattern and said gate electrode wiring obliquely cross each other. 
     
     
       30. A semiconductor device comprising: 
       an element isolation region of shallow trench isolation type, the element isolation region having a trench formed in a surface region of a semiconductor substrate, and in which  
       an isolation film is formed;  
       a gate electrode wiring;  
       a bit line; and  
       element forming regions formed in the surface region of the semiconductor substrate isolated from each other by said element isolation region, each of the element forming regions having a pattern with a width at a central portion of the element forming region and with a width at both edge portions of the element forming region narrower than the width at the central portion, wherein  
       one of a source diffusion layer and a drain diffusion layer of a MOS transistor is formed in the central portion of the element forming region, said one of the source diffusion layer and the drain diffusion layer of the MOS transistor is electrically connected to the bit line,  
       the other of the source diffusion layer and the drain diffusion layer of the MOS transistor is formed in the edge portions of the element forming region, said other of the source diffusion layer and the drain diffusion layer of the MOS transistor is electrically connected to a storage node of a capacitor, and  
       said gate electrode wiring crosses between the source diffusion layer and the drain diffusion layer.